arm64: zynqmp: Separate SMK-K26 from SM-K26

Starter kit has sdhci0 disabled in HW that's why create separate it from
each other. Issue is if HW disable clk for this IP but IP is enabled in DT
u-boot is trying to access that regs and fails.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2ca02acf09014be1535d5d7448b164dc34e08e67..852b301d634c04dab953210c947350f4b591c84f 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -317,6 +317,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
        zynqmp-mini-qspi-x2-single.dtb          \
        zynqmp-mini-qspi-x2-stacked.dtb         \
        zynqmp-sm-k26-revA.dtb                  \
+       zynqmp-smk-k26-revA.dtb                 \
        zynqmp-sck-kv-g-dp.dtbo                 \
        zynqmp-sck-kv-g-revA.dtbo               \
        zynqmp-sck-kv-g-revB.dtbo               \

diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 02eb9d5a014186b314d5427f24150e5f05d2ea25..e025e6eba252be8d5fa7ccf256ef401460e2ff04 100644 (file)
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * dts file for Xilinx ZynqMP SM-K26/SMK-K26 rev1/B/A
+ * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
  *
  * (C) Copyright 2020, Xilinx, Inc.
  *
@@ -16,11 +16,9 @@
 #include <dt-bindings/phy/phy.h>
 
 / {
-       model = "ZynqMP SM-K26/SMK-K26 Rev1/B/A";
+       model = "ZynqMP SM-K26 Rev1/B/A";
        compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
                     "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
-                    "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
-                    "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
                     "xlnx,zynqmp";
 
        aliases {

diff --git a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
new file mode 100644 (file)
index 0000000..8e91067
--- /dev/null
+++ b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP Z2-VSOM
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/* SD0 only supports 3.3V, no level shifter */
+&sdhci1 { /* FIXME - on CC - MIO 39 - 51 */
+       status = "okay";
+       no-1-8-v;
+       disable-wp;
+       broken-cd;
+       xlnx,mio-bank = <1>;
+       /* Do not run SD in HS mode from bootloader */
+       sdhci-caps-mask = <0 0x200000>;
+       sdhci-caps = <0 0>;
+       max-frequency = <19000000>;
+};

diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts
new file mode 100644 (file)
index 0000000..eb932cd
--- /dev/null
+++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+
+#include "zynqmp-sm-k26-revA.dts"
+
+/ {
+       model = "ZynqMP SMK-K26 Rev1/B/A";
+       compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
+                    "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
+                    "xlnx,zynqmp";
+};
+
+&sdhci0 {
+       status = "disabled";
+};

diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index ce4ba02304d67fac9bc115e2957b9417207104d0..2268863e149a850d00c76b750e58d37aa5b769cb 100644 (file)
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -67,7 +67,7 @@ CONFIG_CMD_MTDPARTS_SPREAD=y
 CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA"
+CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA"
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains"
 CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_FAT=y