+2016-05-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ * sysdeps/x86/cacheinfo.c (init_cacheinfo): Check and support
+ non-inclusive caches on Intel processors.
+
2016-05-13 Florian Weimer <fweimer@redhat.com>
* malloc/malloc.c (dumped_main_arena_start)
{
data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid);
+ long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
+ bool inclusive_cache = true;
+
/* Try L3 first. */
level = 3;
shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid);
{
/* Try L2 otherwise. */
level = 2;
- shared = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
+ shared = core;
}
/* Figure out the number of logical threads that share the
}
while (((eax >> 5) & 0x7) != level);
+ /* Check if cache is inclusive of lower cache levels. */
+ inclusive_cache = (edx & 0x2) != 0;
+
threads = (eax >> 14) & 0x3ff;
/* If max_cpuid >= 11, THREADS is the maximum number of
threads. */
if (shared > 0 && threads > 0)
shared /= threads;
+
+ /* Account for non-inclusive L2 and L3 caches. */
+ if (level == 3 && !inclusive_cache)
+ shared += core;
}
/* This spells out "AuthenticAMD". */
else if (is_amd)