EDAC/fsl_ddr: Fix bad bit shift operations

Fix undefined behavior caused by left-shifting a negative value in the
expression:

    cap_high ^ (1 << (bad_data_bit - 32))

The variable bad_data_bit ranges from 0 to 63. When it is less than 32,
bad_data_bit - 32 becomes negative, and left-shifting by a negative
value in C is undefined behavior.

Fix this by combining cap_high and cap_low into a 64-bit variable.

  [ bp: Massage commit message, simplify error bits handling. ]

Fixes: ea2eb9a8b620 ("EDAC, fsl-ddr: Separate FSL DDR driver from MPC85xx")
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20241016-imx95_edac-v3-3-86ae6fc2756a@nxp.com

diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index 7a9fb1202f1a0961f1d25ff1c98655fa3aa77b98..fe822cb9b562d8cf92d7389f6607915a385be69a 100644 (file)
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -328,21 +328,25 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
         * TODO: Add support for 32-bit wide buses
         */
        if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
+               u64 cap = (u64)cap_high << 32 | cap_low;
+               u32 s = syndrome;
+
                sbe_ecc_decode(cap_high, cap_low, syndrome,
                                &bad_data_bit, &bad_ecc_bit);
 
-               if (bad_data_bit != -1)
-                       fsl_mc_printk(mci, KERN_ERR,
-                               "Faulty Data bit: %d\n", bad_data_bit);
-               if (bad_ecc_bit != -1)
-                       fsl_mc_printk(mci, KERN_ERR,
-                               "Faulty ECC bit: %d\n", bad_ecc_bit);
+               if (bad_data_bit >= 0) {
+                       fsl_mc_printk(mci, KERN_ERR, "Faulty Data bit: %d\n", bad_data_bit);
+                       cap ^= 1ULL << bad_data_bit;
+               }
+
+               if (bad_ecc_bit >= 0) {
+                       fsl_mc_printk(mci, KERN_ERR, "Faulty ECC bit: %d\n", bad_ecc_bit);
+                       s ^= 1 << bad_ecc_bit;
+               }
 
                fsl_mc_printk(mci, KERN_ERR,
                        "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
-                       cap_high ^ (1 << (bad_data_bit - 32)),
-                       cap_low ^ (1 << bad_data_bit),
-                       syndrome ^ (1 << bad_ecc_bit));
+                       upper_32_bits(cap), lower_32_bits(cap), s);
        }
 
        fsl_mc_printk(mci, KERN_ERR,