arm64: dts: qcom: ipq5332: Add PCIe related nodes

Add phy and controller nodes for pcie0_x1 and pcie1_x2.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250317100029.881286-4-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 69dda757925d310845f700b60a35e84385c0d500..bd28c490415ff61624f6ff0461d79e975f2c397f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -252,6 +252,46 @@
                        #thermal-sensor-cells = <1>;
                };
 
+               pcie0_phy: phy@4b0000 {
+                       compatible = "qcom,ipq5332-uniphy-pcie-phy";
+                       reg = <0x004b0000 0x800>;
+
+                       clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
+                                <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+
+                       resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
+                                <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
+                                <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
+
+                       #clock-cells = <0>;
+
+                       #phy-cells = <0>;
+
+                       num-lanes = <1>;
+
+                       status = "disabled";
+               };
+
+               pcie1_phy: phy@4b1000 {
+                       compatible = "qcom,ipq5332-uniphy-pcie-phy";
+                       reg = <0x004b1000 0x1000>;
+
+                       clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
+                                <&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
+
+                       resets = <&gcc GCC_PCIE3X2_PHY_BCR>,
+                                <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>,
+                                <&gcc GCC_PCIE3X2PHY_PHY_BCR>;
+
+                       #clock-cells = <0>;
+
+                       #phy-cells = <0>;
+
+                       num-lanes = <2>;
+
+                       status = "disabled";
+               };
+
                tlmm: pinctrl@1000000 {
                        compatible = "qcom,ipq5332-tlmm";
                        reg = <0x01000000 0x300000>;
@@ -278,8 +318,8 @@
                        #interconnect-cells = <1>;
                        clocks = <&xo_board>,
                                 <&sleep_clk>,
-                                <0>,
-                                <0>,
+                                <&pcie1_phy>,
+                                <&pcie0_phy>,
                                 <0>;
                };
 
@@ -545,6 +585,214 @@
                                status = "disabled";
                        };
                };
+
+               pcie1: pcie@18000000 {
+                       compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
+                       reg = <0x18000000 0xf1c>,
+                             <0x18000f20 0xa8>,
+                             <0x18001000 0x1000>,
+                             <0x00088000 0x3000>,
+                             <0x18100000 0x1000>,
+                             <0x0008b000 0x1000>;
+                       reg-names = "dbi",
+                                   "elbi",
+                                   "atu",
+                                   "parf",
+                                   "config",
+                                   "mhi";
+                       device_type = "pci";
+                       linux,pci-domain = <1>;
+                       num-lanes = <2>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x00100000>,
+                                <0x02000000 0x0 0x18300000 0x18300000 0x0 0x07d00000>;
+
+                       msi-map = <0x0 &v2m0 0x0 0xffd>;
+
+                       interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi0",
+                                         "msi1",
+                                         "msi2",
+                                         "msi3",
+                                         "msi4",
+                                         "msi5",
+                                         "msi6",
+                                         "msi7",
+                                         "global";
+
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>,
+                                <&gcc GCC_PCIE3X2_AXI_S_CLK>,
+                                <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
+                                <&gcc GCC_PCIE3X2_RCHG_CLK>,
+                                <&gcc GCC_PCIE3X2_AHB_CLK>,
+                                <&gcc GCC_PCIE3X2_AUX_CLK>;
+                       clock-names = "axi_m",
+                                     "axi_s",
+                                     "axi_bridge",
+                                     "rchng",
+                                     "ahb",
+                                     "aux";
+
+                       assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>;
+
+                       assigned-clock-rates = <2000000>;
+
+                       resets = <&gcc GCC_PCIE3X2_PIPE_ARES>,
+                                <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>,
+                                <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>,
+                                <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>,
+                                <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>,
+                                <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>,
+                                <&gcc GCC_PCIE3X2_AUX_CLK_ARES>,
+                                <&gcc GCC_PCIE3X2_AHB_CLK_ARES>;
+                       reset-names = "pipe",
+                                     "sticky",
+                                     "axi_s_sticky",
+                                     "axi_s",
+                                     "axi_m_sticky",
+                                     "axi_m",
+                                     "aux",
+                                     "ahb";
+
+                       phys = <&pcie1_phy>;
+                       phy-names = "pciephy";
+
+                       interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>,
+                                       <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>;
+                       interconnect-names = "pcie-mem", "cpu-pcie";
+
+                       status = "disabled";
+
+                       pcie@0 {
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
+               };
+
+               pcie0: pcie@20000000 {
+                       compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
+                       reg = <0x20000000 0xf1c>,
+                             <0x20000f20 0xa8>,
+                             <0x20001000 0x1000>,
+                             <0x00080000 0x3000>,
+                             <0x20100000 0x1000>,
+                             <0x00083000 0x1000>;
+                       reg-names = "dbi",
+                                   "elbi",
+                                   "atu",
+                                   "parf",
+                                   "config",
+                                   "mhi";
+                       device_type = "pci";
+                       linux,pci-domain = <0>;
+                       num-lanes = <1>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x00100000>,
+                                <0x02000000 0x0 0x20300000 0x20300000 0x0 0x0fd00000>;
+
+                       msi-map = <0x0 &v2m0 0x0 0xffd>;
+
+                       interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi0",
+                                         "msi1",
+                                         "msi2",
+                                         "msi3",
+                                         "msi4",
+                                         "msi5",
+                                         "msi6",
+                                         "msi7",
+                                         "global";
+
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
+                                <&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
+                                <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
+                                <&gcc GCC_PCIE3X1_0_RCHG_CLK>,
+                                <&gcc GCC_PCIE3X1_0_AHB_CLK>,
+                                <&gcc GCC_PCIE3X1_0_AUX_CLK>;
+                       clock-names = "axi_m",
+                                     "axi_s",
+                                     "axi_bridge",
+                                     "rchng",
+                                     "ahb",
+                                     "aux";
+
+                       assigned-clocks = <&gcc GCC_PCIE3X1_0_AUX_CLK>;
+
+                       assigned-clock-rates = <2000000>;
+
+                       resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>,
+                                <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>,
+                                <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>,
+                                <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>,
+                                <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>,
+                                <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>,
+                                <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>,
+                                <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>;
+                       reset-names = "pipe",
+                                     "sticky",
+                                     "axi_s_sticky",
+                                     "axi_s",
+                                     "axi_m_sticky",
+                                     "axi_m",
+                                     "aux",
+                                     "ahb";
+
+                       phys = <&pcie0_phy>;
+                       phy-names = "pciephy";
+
+                       interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>,
+                                       <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>;
+                       interconnect-names = "pcie-mem", "cpu-pcie";
+
+                       status = "disabled";
+
+                       pcie@0 {
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
+               };
        };
 
        thermal-zones {