[intel] Explicitly enable descriptor queues

On i350 the datasheet contradicts itself in stating that the default
value of RXDCTL.ENABLE for queue zero is both set (according to the
"Receive Initialization" section) and unset (according to the "Receive
Descriptor Control - RXDCTL" section).  Empirical evidence suggests
that the default value is unset.

Explicitly enable both transmit and receive queues to avoid any
ambiguity.

Signed-off-by: Michael Brown <mcb30@ipxe.org>

diff --git a/src/drivers/net/intel.c b/src/drivers/net/intel.c
index 8153e0953d523fcc607b0328e88c2770e3b36657..1fdce1cbf6558e22a9d6c1212c2698d163f1c3c2 100644 (file)
--- a/src/drivers/net/intel.c
+++ b/src/drivers/net/intel.c
@@ -363,6 +363,7 @@ static void intel_check_link ( struct net_device *netdev ) {
 static int intel_create_ring ( struct intel_nic *intel,
                               struct intel_ring *ring ) {
        physaddr_t address;
+       uint32_t dctl;
 
        /* Allocate descriptor ring.  Align ring on its own size to
         * prevent any possible page-crossing errors due to hardware
@@ -393,6 +394,11 @@ static int intel_create_ring ( struct intel_nic *intel,
        writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
        writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
 
+       /* Enable ring */
+       dctl = readl ( intel->regs + ring->reg + INTEL_xDCTL );
+       dctl |= INTEL_xDCTL_ENABLE;
+       writel ( dctl, intel->regs + ring->reg + INTEL_xDCTL );
+
        DBGC ( intel, "INTEL %p ring %05x is at [%08llx,%08llx)\n",
               intel, ring->reg, ( ( unsigned long long ) address ),
               ( ( unsigned long long ) address + ring->len ) );

diff --git a/src/drivers/net/intel.h b/src/drivers/net/intel.h
index 6f941d178f33138be802083c2e23c5df05479322..b38a7139093b993da8ecae0fb1e46d7675e70ec6 100644 (file)
--- a/src/drivers/net/intel.h
+++ b/src/drivers/net/intel.h
@@ -170,6 +170,10 @@ enum intel_descriptor_status {
 /** Receive/Transmit Descriptor Tail (offset) */
 #define INTEL_xDT 0x18
 
+/** Receive/Transmit Descriptor Control (offset) */
+#define INTEL_xDCTL 0x28
+#define INTEL_xDCTL_ENABLE     0x02000000UL    /**< Queue enable */
+
 /** Receive Descriptor Head */
 #define INTEL_RDH ( INTEL_RD + INTEL_xDH )