perf/x86/intel: Support hybrid PMU with multiple atom uarchs

The upcoming ARL-H hybrid processor contains 2 different atom uarchs
which have different PMU capabilities. To distinguish these atom uarchs,
CPUID.1AH.EAX[23:0] defines a native model ID which can be used to
uniquely identify the uarch of the core by combining with core type.

Thus a 3rd hybrid pmu type "hybrid_tiny" is defined to mark the 2nd
atom uarch. The helper find_hybrid_pmu_for_cpu() would compare the
hybrid pmu type and dynamically read core native id from cpu to identify
the corresponding hybrid pmu structure.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Link: https://lkml.kernel.org/r/20240820073853.1974746-4-dapeng1.mi@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index d879478db3f572077d69fe2cc290d3c3f236fe16..6b9884ee96e993c12e81c05da096c7fad53dc211 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4924,17 +4924,26 @@ static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void)
 
        /*
         * This essentially just maps between the 'hybrid_cpu_type'
-        * and 'hybrid_pmu_type' enums:
+        * and 'hybrid_pmu_type' enums except for ARL-H processor
+        * which needs to compare atom uarch native id since ARL-H
+        * contains two different atom uarchs.
         */
        for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
                enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type;
+               u32 native_id;
 
-               if (cpu_type == HYBRID_INTEL_CORE &&
-                   pmu_type == hybrid_big)
-                       return &x86_pmu.hybrid_pmu[i];
-               if (cpu_type == HYBRID_INTEL_ATOM &&
-                   pmu_type == hybrid_small)
+               if (cpu_type == HYBRID_INTEL_CORE && pmu_type == hybrid_big)
                        return &x86_pmu.hybrid_pmu[i];
+               if (cpu_type == HYBRID_INTEL_ATOM) {
+                       if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small)
+                               return &x86_pmu.hybrid_pmu[i];
+
+                       native_id = get_this_hybrid_cpu_native_id();
+                       if (native_id == skt_native_id && pmu_type == hybrid_small)
+                               return &x86_pmu.hybrid_pmu[i];
+                       if (native_id == cmt_native_id && pmu_type == hybrid_tiny)
+                               return &x86_pmu.hybrid_pmu[i];
+               }
        }
 
        return NULL;
@@ -6238,8 +6247,9 @@ static inline int intel_pmu_v6_addr_offset(int index, bool eventsel)
 }
 
 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = {
-       { hybrid_small, "cpu_atom" },
-       { hybrid_big, "cpu_core" },
+       { hybrid_small, "cpu_atom" },
+       { hybrid_big,   "cpu_core" },
+       { hybrid_tiny,  "cpu_lowpower" },
 };
 
 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
@@ -6272,7 +6282,7 @@ static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
                                                        0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
 
                pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
-               if (pmu->pmu_type & hybrid_small) {
+               if (pmu->pmu_type & hybrid_small_tiny) {
                        pmu->intel_cap.perf_metrics = 0;
                        pmu->intel_cap.pebs_output_pt_available = 1;
                        pmu->mid_ack = true;

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index fdd7d0369d42cbe13f4646a246d1e39880723525..909467d6d7edd4e7b1e4e0b6734f703e8137dfc1 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -668,6 +668,12 @@ enum {
 #define PERF_PEBS_DATA_SOURCE_GRT_MAX  0x10
 #define PERF_PEBS_DATA_SOURCE_GRT_MASK (PERF_PEBS_DATA_SOURCE_GRT_MAX - 1)
 
+/*
+ * CPUID.1AH.EAX[31:0] uniquely identifies the microarchitecture
+ * of the core. Bits 31-24 indicates its core type (Core or Atom)
+ * and Bits [23:0] indicates the native model ID of the core.
+ * Core type and native model ID are defined in below enumerations.
+ */
 enum hybrid_cpu_type {
        HYBRID_INTEL_NONE,
        HYBRID_INTEL_ATOM       = 0x20,
@@ -676,13 +682,23 @@ enum hybrid_cpu_type {
 
 #define X86_HYBRID_PMU_ATOM_IDX                0
 #define X86_HYBRID_PMU_CORE_IDX                1
+#define X86_HYBRID_PMU_TINY_IDX                2
 
 enum hybrid_pmu_type {
        not_hybrid,
        hybrid_small            = BIT(X86_HYBRID_PMU_ATOM_IDX),
        hybrid_big              = BIT(X86_HYBRID_PMU_CORE_IDX),
+       hybrid_tiny             = BIT(X86_HYBRID_PMU_TINY_IDX),
+
+       /* The belows are only used for matching */
+       hybrid_big_small        = hybrid_big   | hybrid_small,
+       hybrid_small_tiny       = hybrid_small | hybrid_tiny,
+       hybrid_big_small_tiny   = hybrid_big   | hybrid_small_tiny,
+};
 
-       hybrid_big_small        = hybrid_big | hybrid_small, /* only used for matching */
+enum atom_native_id {
+       cmt_native_id           = 0x2,  /* Crestmont */
+       skt_native_id           = 0x3,  /* Skymont */
 };
 
 struct x86_hybrid_pmu {