drm/amd/display: clean up some inconsistent indentings

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn35/dcn35_hwseq.c:159 dcn35_init_hw() warn: inconsistent indentig

Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c
index 666e2809d9dc5e7cc73d92416b3fc9810fc2ca29..0258491432548ee5946466a83a929b3db41133f5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c
@@ -155,22 +155,22 @@ void dcn35_init_hw(struct dc *dc)
                res_pool->ref_clocks.xtalin_clock_inKhz =
                                dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-                       if (res_pool->dccg && res_pool->hubbub) {
-
-                               (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
-                                               dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
-                                               &res_pool->ref_clocks.dccg_ref_clock_inKhz);
-
-                               (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
-                                               res_pool->ref_clocks.dccg_ref_clock_inKhz,
-                                               &res_pool->ref_clocks.dchub_ref_clock_inKhz);
-                       } else {
-                               // Not all ASICs have DCCG sw component
-                               res_pool->ref_clocks.dccg_ref_clock_inKhz =
-                                               res_pool->ref_clocks.xtalin_clock_inKhz;
-                               res_pool->ref_clocks.dchub_ref_clock_inKhz =
-                                               res_pool->ref_clocks.xtalin_clock_inKhz;
-                       }
+               if (res_pool->dccg && res_pool->hubbub) {
+
+                       (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+                               dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+                               &res_pool->ref_clocks.dccg_ref_clock_inKhz);
+
+                       (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+                               res_pool->ref_clocks.dccg_ref_clock_inKhz,
+                               &res_pool->ref_clocks.dchub_ref_clock_inKhz);
+               } else {
+                       // Not all ASICs have DCCG sw component
+                       res_pool->ref_clocks.dccg_ref_clock_inKhz =
+                               res_pool->ref_clocks.xtalin_clock_inKhz;
+                       res_pool->ref_clocks.dchub_ref_clock_inKhz =
+                               res_pool->ref_clocks.xtalin_clock_inKhz;
+               }
        } else
                ASSERT_CRITICAL(false);