read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
ret = submit_descs(nandc);
-@@ -2864,7 +2815,7 @@ static int qcom_param_page_type_exec(str
+@@ -2862,14 +2813,14 @@ static int qcom_param_page_type_exec(str
+
+ reg_base = NAND_READ_LOCATION_0;
+
+- if (nandc->props->qpic_v2)
++ if (nandc->props->qpic_version2)
+ reg_base = NAND_READ_LOCATION_LAST_CW_0;
+
+ ret = qcom_parse_instructions(chip, subop, &q_op);
if (ret)
return ret;
nandc->buf_count = 0;
nandc->buf_start = 0;
-@@ -2872,38 +2823,38 @@ static int qcom_param_page_type_exec(str
+@@ -2877,52 +2828,52 @@ static int qcom_param_page_type_exec(str
clear_read_regs(nandc);
clear_bam_transaction(nandc);
}
instr = q_op.data_instr;
-@@ -2912,9 +2863,9 @@ static int qcom_param_page_type_exec(str
+ op_id = q_op.data_instr_idx;
+ len = nand_subop_get_data_len(subop, op_id);
- nandc_set_read_loc(chip, 0, 0, 0, len, 1);
+- if (nandc->props->qpic_v2)
++ if (nandc->props->qpic_version2)
+ nandc_set_read_loc_last(chip, reg_base, 0, len, 1);
+ else
+ nandc_set_read_loc_first(chip, reg_base, 0, len, 1);
- if (!nandc->props->qpic_v2) {
- write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
}
nandc->buf_count = 512;
-@@ -2926,9 +2877,10 @@ static int qcom_param_page_type_exec(str
+@@ -2934,9 +2885,10 @@ static int qcom_param_page_type_exec(str
nandc->buf_count, 0);
/* restore CMD1 and VLD regs */
}
ret = submit_descs(nandc);
-@@ -3017,7 +2969,7 @@ static const struct nand_controller_ops
+@@ -3025,7 +2977,7 @@ static const struct nand_controller_ops
static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
{
if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
dma_unmap_single(nandc->dev, nandc->reg_read_dma,
MAX_REG_RD *
-@@ -3070,7 +3022,7 @@ static int qcom_nandc_alloc(struct qcom_
+@@ -3078,7 +3030,7 @@ static int qcom_nandc_alloc(struct qcom_
if (!nandc->reg_read_buf)
return -ENOMEM;
nandc->reg_read_dma =
dma_map_single(nandc->dev, nandc->reg_read_buf,
MAX_REG_RD *
-@@ -3151,15 +3103,15 @@ static int qcom_nandc_setup(struct qcom_
+@@ -3159,15 +3111,15 @@ static int qcom_nandc_setup(struct qcom_
u32 nand_ctrl;
/* kill onenand */
nand_ctrl = nandc_read(nandc, NAND_CTRL);
/*
-@@ -3176,7 +3128,7 @@ static int qcom_nandc_setup(struct qcom_
+@@ -3184,7 +3136,7 @@ static int qcom_nandc_setup(struct qcom_
}
/* save the original values of these registers */
nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1));
nandc->vld = NAND_DEV_CMD_VLD_VAL;
}
-@@ -3349,7 +3301,7 @@ static int qcom_nandc_parse_dt(struct pl
+@@ -3357,7 +3309,7 @@ static int qcom_nandc_parse_dt(struct pl
struct device_node *np = nandc->dev->of_node;
int ret;
ret = of_property_read_u32(np, "qcom,cmd-crci",
&nandc->cmd_crci);
if (ret) {
-@@ -3474,30 +3426,30 @@ static void qcom_nandc_remove(struct pla
+@@ -3482,30 +3434,30 @@ static void qcom_nandc_remove(struct pla
static const struct qcom_nandc_props ipq806x_nandc_props = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
if (ret) {
dev_err(nandc->dev, "failure in submitting misc descriptor\n");
goto err_out;
-@@ -2820,8 +2820,8 @@ static int qcom_param_page_type_exec(str
+@@ -2825,8 +2825,8 @@ static int qcom_param_page_type_exec(str
nandc->buf_count = 0;
nandc->buf_start = 0;
host->use_ecc = false;
nandc->regs->cmd = q_op.cmd_reg;
nandc->regs->addr0 = 0;
-@@ -2864,8 +2864,8 @@ static int qcom_param_page_type_exec(str
- nandc_set_read_loc(chip, 0, 0, 0, len, 1);
+@@ -2872,8 +2872,8 @@ static int qcom_param_page_type_exec(str
+ nandc_set_read_loc_first(chip, reg_base, 0, len, 1);
if (!nandc->props->qpic_version2) {
- write_reg_dma(nandc, &nandc->regs->vld, NAND_DEV_CMD_VLD, 1, 0);
}
nandc->buf_count = 512;
-@@ -2873,17 +2873,17 @@ static int qcom_param_page_type_exec(str
+@@ -2881,17 +2881,17 @@ static int qcom_param_page_type_exec(str
config_nand_single_cw_page_read(chip, false, 0);
if (ret) {
dev_err(nandc->dev, "failure in submitting param page descriptor\n");
goto err_out;
-@@ -3067,7 +3067,7 @@ static int qcom_nandc_alloc(struct qcom_
+@@ -3075,7 +3075,7 @@ static int qcom_nandc_alloc(struct qcom_
* maximum codeword size
*/
nandc->max_cwperpage = 1;
/*
* when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
* an erased CW, and reports an erased CW in NAND_ERASED_CW_DETECT_STATUS.
-@@ -2967,141 +2022,14 @@ static const struct nand_controller_ops
+@@ -2975,141 +2030,14 @@ static const struct nand_controller_ops
.exec_op = qcom_nand_exec_op,
};
/* kill onenand */
if (!nandc->props->nandc_part_of_qpic)
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
-@@ -3240,7 +2168,7 @@ static int qcom_nand_host_init_and_regis
+@@ -3248,7 +2176,7 @@ static int qcom_nand_host_init_and_regis
chip->legacy.block_bad = qcom_nandc_block_bad;
chip->legacy.block_markbad = qcom_nandc_block_markbad;
chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA |
NAND_SKIP_BBTSCAN;
-@@ -3323,17 +2251,21 @@ static int qcom_nandc_parse_dt(struct pl
+@@ -3331,17 +2259,21 @@ static int qcom_nandc_parse_dt(struct pl
static int qcom_nandc_probe(struct platform_device *pdev)
{
struct qcom_nand_controller *nandc;