]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: ti: k3-am62: Add GPMC and ELM nodes
authorNitin Yadav <n-yadav@ti.com>
Sat, 22 Jun 2024 11:59:56 +0000 (14:59 +0300)
committerVignesh Raghavendra <vigneshr@ti.com>
Mon, 1 Jul 2024 16:06:06 +0000 (21:36 +0530)
Add GPMC and ELM device tree nodes for AM62 SoC family.

Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240622-am62lp-sk-nand-v1-1-caee496eaf42@kernel.org
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
arch/arm64/boot/dts/ti/k3-am62.dtsi

index 00776a9987c135f2a862e89128a9d51fbc66aac2..e7e7cdc24e3d484a693af75a041d6272579d6627 100644 (file)
                status = "disabled";
        };
 
+       gpmc0: memory-controller@3b000000 {
+               compatible = "ti,am64-gpmc";
+               power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 80 0>;
+               clock-names = "fck";
+               reg = <0x00 0x03b000000 0x00 0x400>,
+                     <0x00 0x050000000 0x00 0x8000000>;
+               reg-names = "cfg", "data";
+               interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+               gpmc,num-cs = <3>;
+               gpmc,num-waitpins = <2>;
+               #address-cells = <2>;
+               #size-cells = <1>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               status = "disabled";
+       };
+
+       elm0: ecc@25010000 {
+               compatible = "ti,am64-elm";
+               reg = <0x00 0x25010000 0x00 0x2000>;
+               interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 54 0>;
+               clock-names = "fck";
+               status = "disabled";
+       };
 };
index f0781f2bea29806e1485d1b8d53f2342d124dcae..bfb55ca113239be4367a1cf8edf219187fafa8a0 100644 (file)
                         <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
                         <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
                         <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
+                        <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
                         <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
                         <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
                         <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
                         <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
                         <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
+                        <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
                         <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
                         <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
                         <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */