RISC-V: Enable pressure-aware scheduling by default.

this patch enables pressure-aware scheduling for riscv.  There have been
various requests for it so I figured I'd just go ahead and send
the patch.

There is some slight regression in code quality for a number of
vector tests where we spill more due to different instructions order.
The ones I looked at were a mix of bad luck and/or brittle tests.
Comparing the size of the generated assembly or the number of vsetvls
for SPECint also didn't show any immediate benefit but that's obviously
not a very fine-grained analysis.

As cost and scheduling models mature I expect the situation to improve
and for now I think it's generally favorable to enable pressure-aware
scheduling so we can work with it rather than trying to find every
possible problem in advance.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add -fsched-pressure.
	* config/riscv/riscv.cc (riscv_option_override): Set sched
	pressure algorithm.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/narrow_constraint-1.c: Add
	-fno-sched-pressure.
	* gcc.target/riscv/rvv/base/narrow_constraint-17.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-18.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-19.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-20.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-21.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-22.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-23.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-24.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-25.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-26.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-27.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-28.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-29.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-30.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-31.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-4.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-5.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-8.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-9.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Ditto.

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 4737dcd44a13bd2dc5eb060890abc5d308fd9957..82330110740c329435a55c96e3945acf02bc340c 100644 (file)
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -2016,6 +2016,8 @@ riscv_get_valid_option_values (int option_code,
 static const struct default_options riscv_option_optimization_table[] =
   {
     { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
+    /* Enable -fsched-pressure starting at -O1.  */
+    { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
     { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
 #if TARGET_DEFAULT_ASYNC_UNWIND_TABLES == 1
     { OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 },

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0f60ffe5f60b425bd712995d527b5e0e497c512b..480f31244960990adce60d9d22eb717d681ed31b 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -65,6 +65,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "cfgloop.h"
 #include "cfgrtl.h"
 #include "sel-sched.h"
+#include "sched-int.h"
 #include "fold-const.h"
 #include "gimple-iterator.h"
 #include "gimple-expr.h"
@@ -7096,6 +7097,10 @@ riscv_option_override (void)
     sorry (
       "Current RISC-V GCC cannot support VLEN greater than 4096bit for 'V' Extension");
 
+  SET_OPTION_IF_UNSET (&global_options, &global_options_set,
+                      param_sched_pressure_algorithm,
+                      SCHED_PRESSURE_MODEL);
+
   /* Convert -march to a chunks count.  */
   riscv_vector_chunks = riscv_convert_vector_bits ();
 }

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c
index 0cdf60cde0678bd305e82cba4d3e5316bdcb94e3..02d155dc5bf27f2fa7a53180913fc86c65135f17 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c
index 97df21dd743cf314d8fbd668f25fa02fe392907d..35ef18817fae7cd8abd89346fb75611e057c4322 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c
index 56c95d9c884e91db72d394db2333b7a59a2db6db..1c17b763fabcfebc88456b4f3f9f3dd754b75d66 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c
index d50e497d6c975aa2719d987ababcee666ccac2f8..923bc27b36b97a1baecc0a49f8f64a051f415907 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c
index 4e77c51d0580c71b0ca6dec690f7ae6d310a6de5..6dd1b84678bbc71a69eab3874c8c642d324fa92a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c
index 4f7efd508b16ad9fb3e9838b7701a1b341a67592..ecf6d267fdb95189911ec8566d3de82dc75e5c44 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c
index 92084be99b2645573dffd857d7961eef741a1e6f..2018607959345036b8247aa94cec5b1571e6b49b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c
index f9817caca1e4217c9f26fb83c9cae296f5f8d261..847d27cc76018587cb939b3ebc72de90c1f12177 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c
index 62d1f6dddd528541337e2d2c58994961b441acbd..603bfa20f82cc94cdf91d60e4b6002cefbfdde76 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c
index 250c3fdb89af7d952e31da75646f337b18d31386..4f295ecaaafbb56f522dfe35b31a84a084dddb36 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c
index 72e2d210c0550fba5dffe833945c48a72e8c4f13..1a652399f87f95930fad79cf71d3f545e14ecdbf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c
index 0842700475cad572969140b9e7f88948ce5ed967..4d70a4c39fdf92792bf26971312e84fb03bfde79 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c
index 9c1eddfac7e5ea3bdf77a3ea7c3b07d5db476048..c625d96a94c7b0f19fc35a26e41bc08d8275d9ad 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c
index 6988c24bd9220344d2bb2a1f3679715b74593f00..109ebc84112d2e74312fc6902cb3dbb88cb92f80 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c
index fe181de4d5613c87680796b7a2aafdf99d6c2494..b993e480765fe584deff3b5a3b060f9417c1f9d6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c
index ae5b4ed69131195061789c7cb35dd3da4c3a7f0e..d0bf4a80c9e4c2ec04b10afeaf65da909d1258f1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c
index 28971a0aad8cf3e84b2498f952cac1f3058367f2..273f15a21ab02d9ce03578a93fe3f990a49ca738 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c
index 26675bcc87c79977dd9b303b4051f21ab4af4796..d75dc77863846c673f357f23bdf31c4ca4f3d587 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c
index 0dac85a3203a363ebd036db7af72af58496653fd..c96ab59888340c3b06ddded9254eab908b54108e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c
index 448ca859dbbf4c5a093e65070aa779497a68e39a..53130d32606843ace256aa6461dd41303519a642 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
index cf6470cea0d30b283b63f64d2f3482ba41fcf382..fba44d999b63099cac2b84c6bc5f10ec7bd3155b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
index 4e2a717197b97e31f964a33ae716f6cee6f04c0e..5aabdef4acad0db5b4d0f96afd2363ae531cb13b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
index 026b40944c5c79ca7d4ff5c70b7f5f4b7c9acb9a..6db0f0b1c51c4894c41e5840b44700de3d621d53 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
index ca57ecad7cfd95f9d61a93753ff7fddef203cf73..5e5e07b37c2fc9e5327c36ecf4b1b4860c1030a0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
index a01b39184047fe3d3816292decbfce64f4196dbd..119e41e23b80055f6d59479880070fad0ca0b19a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"