# and Cc: the <u-boot@lists.denx.de> mailing list. #
# #
# Note: lists sorted by Maintainer Name #
+ # Note: These are the maintainers for specific *boards*. The #
+ # custodians for general architectures and subsystems can #
+ # be found here -- http://www.denx.de/wiki/U-Boot/Custodians #
+ # #
#########################################################################
Stefan Roese <sr@denx.de>
+ a3m071 MPC5200
+
P3M7448 MPC7448
uc100 MPC857
trizepsiv xscale/pxa
twister omap3
vision2 i.MX51
+ woodburn i.MX35
Lukasz Dalek <luk0104@gmail.com>
apx4devkit i.MX28
- Luka Perkov <uboot@lukaperkov.net>
+ Luka Perkov <luka@openwrt.org>
ib62x0 ARM926EJS
iconnect ARM926EJS
VERSION = 2013
PATCHLEVEL = 01
SUBLEVEL =
- EXTRAVERSION = -rc1
+ EXTRAVERSION = -rc2
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
OBJS = $(CPUDIR)/start.o
ifeq ($(CPU),x86)
- OBJS += $(CPUDIR)/start16.o
- OBJS += $(CPUDIR)/resetvec.o
+ RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/start16.o
+ RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/resetvec.o
endif
ifeq ($(CPU),ppc4xx)
OBJS += $(CPUDIR)/resetvec.o
OBJS += $(CPUDIR)/resetvec.o
endif
- OBJS := $(addprefix $(obj),$(OBJS))
+ OBJS := $(addprefix $(obj),$(OBJS) $(RESET_OBJS-))
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
LIBS-y += drivers/net/phy/libphy.o
LIBS-y += drivers/pci/libpci.o
LIBS-y += drivers/pcmcia/libpcmcia.o
- LIBS-y += drivers/power/libpower.o
+ LIBS-y += drivers/power/libpower.o \
+ drivers/power/fuel_gauge/libfuel_gauge.o \
+ drivers/power/pmic/libpmic.o \
+ drivers/power/battery/libbattery.o
LIBS-y += drivers/spi/libspi.o
LIBS-y += drivers/dfu/libdfu.o
ifeq ($(CPU),mpc83xx)
endif
LIBS-y += drivers/rtc/librtc.o
LIBS-y += drivers/serial/libserial.o
+LIBS-y += drivers/sound/libsound.o
LIBS-$(CONFIG_GENERIC_LPC_TPM) += drivers/tpm/libtpm.o
LIBS-y += drivers/twserial/libtws.o
LIBS-y += drivers/usb/eth/libusb_eth.o
LIBS-y += drivers/usb/gadget/libusb_gadget.o
LIBS-y += drivers/usb/host/libusb_host.o
LIBS-y += drivers/usb/musb/libusb_musb.o
+ LIBS-y += drivers/usb/musb-new/libusb_musb-new.o
LIBS-y += drivers/usb/phy/libusb_phy.o
LIBS-y += drivers/usb/ulpi/libusb_ulpi.o
LIBS-y += drivers/video/libvideo.o
ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
BOARD_SIZE_CHECK = \
@actual=`wc -c $@ | awk '{print $$1}'`; \
- limit=$(CONFIG_BOARD_SIZE_LIMIT); \
+ limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
if test $$actual -gt $$limit; then \
- echo "$@ exceeds file size limit:"; \
- echo " limit: $$limit bytes"; \
- echo " actual: $$actual bytes"; \
- echo " excess: $$((actual - limit)) bytes"; \
+ echo "$@ exceeds file size limit:" >&2 ; \
+ echo " limit: $$limit bytes" >&2 ; \
+ echo " actual: $$actual bytes" >&2 ; \
+ echo " excess: $$((actual - limit)) bytes" >&2; \
exit 1; \
fi
else
ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
+ ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET))
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
# enable combined SPL/u-boot/dtb rules for tegra
$(obj)u-boot.ldr.srec: $(obj)u-boot.ldr
$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary
+ #
+ # U-Boot entry point, needed for booting of full-blown U-Boot
+ # from the SPL U-Boot version.
+ #
+ ifndef CONFIG_SYS_UBOOT_START
+ CONFIG_SYS_UBOOT_START := 0
+ endif
+
$(obj)u-boot.img: $(obj)u-boot.bin
$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
- -O u-boot -a $(CONFIG_SYS_TEXT_BASE) -e 0 \
+ -O u-boot -a $(CONFIG_SYS_TEXT_BASE) \
+ -e $(CONFIG_SYS_UBOOT_START) \
-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
- $(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
- cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-ubl.bin
- $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
- -e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin $(obj)u-boot.ubl
- rm $(obj)u-boot-ubl.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
+ $(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin
+ $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
+ -e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
+
$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
$(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
-T aisimage \
rm $(obj)spl/u-boot-spl-pad.bin
endif
+ $(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
+ cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@
+
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
echo '*** Your board is configured for THUMB mode.'; \
false; \
fi
+
+ # GCC 3.x is reported to have problems generating the type of relocation
+ # that U-Boot wants.
+ # See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
+ checkgcc4:
+ @if test $(call cc-version) -lt 0400; then \
+ echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
+ false; \
+ fi
+
#
# Auto-generate the autoconf.mk file (which is included by all makefiles)
#
@rm -f $(obj)include/generated/asm-offsets.h
@rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
- @$(MAKE) -C doc/DocBook/ cleandocs
+ @$(MAKE) -s -C doc/DocBook/ cleandocs
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
@rm -f $(obj)MLO
+ @rm -f $(obj)SPL
@rm -f $(obj)tools/xway-swap-bytes
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
who contributed the specific port. The MAINTAINERS file lists board
maintainers.
+ Note: There is no CHANGELOG file in the actual U-Boot source tree;
+ it can be created dynamically from the Git log using:
+
+ make CHANGELOG
+
Where to get help:
==================
CONFIG_CMD_EDITENV edit env variable
CONFIG_CMD_EEPROM * EEPROM read/write support
CONFIG_CMD_ELF * bootelf, bootvx
+ CONFIG_CMD_ENV_CALLBACK * display details about env callbacks
+ CONFIG_CMD_ENV_FLAGS * display details about env flags
CONFIG_CMD_EXPORTENV * export the environment
CONFIG_CMD_EXT2 * ext2 command support
CONFIG_CMD_EXT4 * ext4 command support
CONFIG_CMD_FDOS * Dos diskette Support
CONFIG_CMD_FLASH flinfo, erase, protect
CONFIG_CMD_FPGA FPGA device initialization support
+ CONFIG_CMD_GETTIME * Get time since boot
CONFIG_CMD_GO * the 'go' command (exec code)
CONFIG_CMD_GREPENV * search environment
+ CONFIG_CMD_HASH * calculate hash / digest
CONFIG_CMD_HWFLOW * RTS/CTS hw flow control
CONFIG_CMD_I2C * I2C serial bus support
CONFIG_CMD_IDE * IDE harddisk support
CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network
host
CONFIG_CMD_PORTIO * Port I/O
+ CONFIG_CMD_READ * Read raw data from partition
CONFIG_CMD_REGINFO * Register dump
CONFIG_CMD_RUN run command in env variable
CONFIG_CMD_SAVES * save S record dump
boot. See the documentation file README.video for a
description of this variable.
+ CONFIG_VIDEO_VGA
+
+ Enable the VGA video / BIOS for x86. The alternative if you
+ are using coreboot is to use the coreboot frame buffer
+ driver.
+
+
- Keyboard Support:
CONFIG_KEYBOARD
Normally display is black on white background; define
CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
-
+ CONFIG_LCD_ALIGNMENT
+
+ Normally the LCD is page-aligned (tyically 4KB). If this is
+ defined then the LCD will be aligned to this value instead.
+ For ARM it is sometimes useful to use MMU_SECTION_SIZE
+ here, since it is cheaper to change data cache settings on
+ a per-section basis.
+
+ CONFIG_CONSOLE_SCROLL_LINES
+
+ When the console need to be scrolled, this is the number of
+ lines to scroll by. It defaults to 1. Increasing this makes
+ the console jump but can help speed up operation when scrolling
+ is slow.
+
+ CONFIG_LCD_BMP_RLE8
+
+ Support drawing of RLE8-compressed bitmaps on the LCD.
+
+ CONFIG_I2C_EDID
+
+ Enables an 'i2c edid' command which can read EDID
+ information over I2C from an attached LCD display.
+
-
- Splash Screen Support: CONFIG_SPLASH_SCREEN
If this option is set, the environment is checked for
serial# is unaffected by this, i. e. it remains
read-only.]
+ The same can be accomplished in a more flexible way
+ for any variable by configuring the type of access
+ to allow for those variables in the ".flags" variable
+ or define CONFIG_ENV_FLAGS_LIST_STATIC.
+
- Protected RAM:
CONFIG_PRAM
HERMES, IP860, RPXlite, LWMON,
FLAGADM, TQM8260
+ - Access to physical memory region (> 4GB)
+ Some basic support is provided for operations on memory not
+ normally accessible to U-Boot - e.g. some architectures
+ support access to more than 4GB of memory on 32-bit
+ machines using physical address extension or similar.
+ Define CONFIG_PHYSMEM to access this basic support, which
+ currently only supports clearing the memory.
+
- Error Recovery:
CONFIG_PANIC_HANG
A better solution is to properly configure the firewall,
but sometimes that is not allowed.
+ - Hashing support:
+ CONFIG_CMD_HASH
+
+ This enables a generic 'hash' command which can produce
+ hashes / digests from a few algorithms (e.g. SHA1, SHA256).
+
+ CONFIG_HASH_VERIFY
+
+ Enable the hash verify command (hash -v). This adds to code
+ size a little.
+
+ CONFIG_SHA1 - support SHA1 hashing
+ CONFIG_SHA256 - support SHA256 hashing
+
+ Note: There is also a sha1sum command, which should perhaps
+ be deprecated in favour of 'hash sha1'.
+
- Show boot progress:
CONFIG_SHOW_BOOT_PROGRESS
-150 common/cmd_nand.c Incorrect FIT image format
151 common/cmd_nand.c FIT image format OK
+ - FIT image support:
+ CONFIG_FIT
+ Enable support for the FIT uImage format.
+
+ CONFIG_FIT_BEST_MATCH
+ When no configuration is explicitly selected, default to the
+ one whose fdt's compatibility field best matches that of
+ U-Boot itself. A match is considered "best" if it matches the
+ most specific compatibility entry of U-Boot's fdt's root node.
+ The order of entries in the configuration's fdt is ignored.
+
- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
CONFIG_SPL_TEXT_BASE
TEXT_BASE for linking the SPL binary.
+ CONFIG_SPL_RELOC_TEXT_BASE
+ Address to relocate to. If unspecified, this is equal to
+ CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
+
CONFIG_SPL_BSS_START_ADDR
Link address for the BSS within the SPL binary.
CONFIG_SPL_STACK
Adress of the start of the stack SPL will use
+ CONFIG_SPL_RELOC_STACK
+ Adress of the start of the stack SPL will use after
+ relocation. If unspecified, this is equal to
+ CONFIG_SPL_STACK.
+
CONFIG_SYS_SPL_MALLOC_START
Starting address of the malloc pool used in SPL.
For ARM, enable an optional function to print more information
about the running system.
+ CONFIG_SPL_INIT_MINIMAL
+ Arch init code should be built for a very small image
+
CONFIG_SPL_LIBCOMMON_SUPPORT
Support for common/libcommon.o in SPL binary
CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
Filename to read to load U-Boot when reading from FAT
+ CONFIG_SPL_NAND_BASE
+ Include nand_base.c in the SPL. Requires
+ CONFIG_SPL_NAND_DRIVERS.
+
+ CONFIG_SPL_NAND_DRIVERS
+ SPL uses normal NAND drivers, not minimal drivers.
+
+ CONFIG_SPL_NAND_ECC
+ Include standard software ECC in the SPL
+
CONFIG_SPL_NAND_SIMPLE
- Support for drivers/mtd/nand/libnand.o in SPL binary
+ Support for NAND boot using simple NAND drivers that
+ expose the cmd_ctrl() interface.
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
CONFIG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses
- to read U-Boot with CONFIG_SPL_NAND_SIMPLE
+ to read U-Boot
CONFIG_SYS_NAND_U_BOOT_OFFS
- Location in NAND for CONFIG_SPL_NAND_SIMPLE to read U-Boot
- from.
+ Location in NAND to read U-Boot from
+
+ CONFIG_SYS_NAND_U_BOOT_DST
+ Location in memory to load U-Boot to
+
+ CONFIG_SYS_NAND_U_BOOT_SIZE
+ Size of image to load
CONFIG_SYS_NAND_U_BOOT_START
- Location in memory for CONFIG_SPL_NAND_SIMPLE to load U-Boot
- to.
+ Entry point in loaded image to jump to
CONFIG_SYS_NAND_HW_ECC_OOBFIRST
Define this if you need to first read the OOB and then the
CONFIG_SPL_LIBGENERIC_SUPPORT
Support for lib/libgeneric.o in SPL binary
+ CONFIG_SPL_TARGET
+ Final target image containing SPL and payload. Some SPLs
+ use an arch-specific makefile fragment instead, for
+ example if more than one image needs to be produced.
+
Modem Support:
--------------
non page size aligned address and this could cause major
problems.
- - CONFIG_SYS_TFTP_LOADADDR:
- Default load address for network file downloads
-
- CONFIG_SYS_LOADS_BAUD_CHANGE:
Enable temporary baudrate change while serial download
cases. This setting can be used to tune behaviour; see
lib/hashtable.c for details.
+ - CONFIG_ENV_FLAGS_LIST_DEFAULT
+ - CONFIG_ENV_FLAGS_LIST_STATIC
+ Enable validation of the values given to enviroment variables when
+ calling env set. Variables can be restricted to only decimal,
+ hexadecimal, or boolean. If CONFIG_CMD_NET is also defined,
+ the variables can also be restricted to IP address or MAC address.
+
+ The format of the list is:
+ type_attribute = [s|d|x|b|i|m]
+ access_atribute = [a|r|o|c]
+ attributes = type_attribute[access_atribute]
+ entry = variable_name[:attributes]
+ list = entry[,list]
+
+ The type attributes are:
+ s - String (default)
+ d - Decimal
+ x - Hexadecimal
+ b - Boolean ([1yYtT|0nNfF])
+ i - IP address
+ m - MAC address
+
+ The access attributes are:
+ a - Any (default)
+ r - Read-only
+ o - Write-once
+ c - Change-default
+
+ - CONFIG_ENV_FLAGS_LIST_DEFAULT
+ Define this to a list (string) to define the ".flags"
+ envirnoment variable in the default or embedded environment.
+
+ - CONFIG_ENV_FLAGS_LIST_STATIC
+ Define this to a list (string) to define validation that
+ should be done if an entry is not found in the ".flags"
+ environment variable. To override a setting in the static
+ list, simply add an entry for the same variable name to the
+ ".flags" variable.
+
+ - CONFIG_ENV_ACCESS_IGNORE_FORCE
+ If defined, don't allow the -f switch to env set override variable
+ access flags.
+
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
following configurations:
be used if available. These functions may be faster under some
conditions but may increase the binary size.
+ - CONFIG_X86_NO_RESET_VECTOR
+ If defined, the x86 reset vector code is excluded. You will need
+ to do this when U-Boot is running from Coreboot.
+
+ - CONFIG_X86_NO_REAL_MODE
+ If defined, x86 real mode code is omitted. This assumes a
+ 32-bit environment where such code is not needed. You will
+ need to do this when U-Boot is running from Coreboot.
+
+
Freescale QE/FMAN Firmware Support:
-----------------------------------
protect - enable or disable FLASH write protection
erase - erase FLASH memory
flinfo - print FLASH memory information
+ nand - NAND memory operations (see doc/README.nand)
bdinfo - print Board Info structure
iminfo - print header information for application image
coninfo - print console devices and informations
only effect after the next boot (yes, that's just like Windoze :-).
+ Callback functions for environment variables:
+ ---------------------------------------------
+
+ For some environment variables, the behavior of u-boot needs to change
+ when their values are changed. This functionailty allows functions to
+ be associated with arbitrary variables. On creation, overwrite, or
+ deletion, the callback will provide the opportunity for some side
+ effect to happen or for the change to be rejected.
+
+ The callbacks are named and associated with a function using the
+ U_BOOT_ENV_CALLBACK macro in your board or driver code.
+
+ These callbacks are associated with variables in one of two ways. The
+ static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
+ in the board configuration to a string that defines a list of
+ associations. The list must be in the following format:
+
+ entry = variable_name[:callback_name]
+ list = entry[,list]
+
+ If the callback name is not specified, then the callback is deleted.
+ Spaces are also allowed anywhere in the list.
+
+ Callbacks can also be associated by defining the ".callbacks" variable
+ with the same list format above. Any association in ".callbacks" will
+ override any association in the static list. You can define
+ CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
+ ".callbacks" envirnoment variable in the default or embedded environment.
+
+
Command Line Parsing:
=====================
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
-
-/* exynos4: return pll clock frequency */
-static unsigned long exynos4_get_pll_clk(int pllreg)
+#include <asm/arch/periph.h>
+
+/* Epll Clock division values to achive different frequency output */
+static struct set_epll_con_val exynos5_epll_div[] = {
+ { 192000000, 0, 48, 3, 1, 0 },
+ { 180000000, 0, 45, 3, 1, 0 },
+ { 73728000, 1, 73, 3, 3, 47710 },
+ { 67737600, 1, 90, 4, 3, 20762 },
+ { 49152000, 0, 49, 3, 3, 9961 },
+ { 45158400, 0, 45, 3, 3, 10381 },
+ { 180633600, 0, 45, 3, 1, 10381 }
+};
+
+/* exynos: return pll clock frequency */
+static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long r, m, p, s, k = 0, mask, fout;
+ unsigned long m, p, s = 0, mask, fout;
unsigned int freq;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
- break;
- case MPLL:
- r = readl(&clk->mpll_con0);
- break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
- break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
/*
* APLL_CON: MIDV [25:16]
* MPLL_CON: MIDV [25:16]
* EPLL_CON: MIDV [24:16]
* VPLL_CON: MIDV [24:16]
+ * BPLL_CON: MIDV [25:16]: Exynos5
*/
- if (pllreg == APLL || pllreg == MPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
mask = 0x3ff;
else
mask = 0x1ff;
return fout;
}
+/* exynos4: return pll clock frequency */
+static unsigned long exynos4_get_pll_clk(int pllreg)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ return exynos_get_pll_clk(pllreg, r, k);
+}
+
/* exynos5: return pll clock frequency */
static unsigned long exynos5_get_pll_clk(int pllreg)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
- unsigned long r, m, p, s, k = 0, mask, fout;
- unsigned int freq, pll_div2_sel, fout_sel;
+ unsigned long r, k = 0, fout;
+ unsigned int pll_div2_sel, fout_sel;
switch (pllreg) {
case APLL:
return 0;
}
- /*
- * APLL_CON: MIDV [25:16]
- * MPLL_CON: MIDV [25:16]
- * EPLL_CON: MIDV [24:16]
- * VPLL_CON: MIDV [24:16]
- * BPLL_CON: MIDV [25:16]
- */
- if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
- mask = 0x3ff;
- else
- mask = 0x1ff;
-
- m = (r >> 16) & mask;
-
- /* PDIV [13:8] */
- p = (r >> 8) & 0x3f;
- /* SDIV [2:0] */
- s = r & 0x7;
-
- freq = CONFIG_SYS_CLK_FREQ;
-
- if (pllreg == EPLL) {
- k = k & 0xffff;
- /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 65536) * (freq / (p * (1 << s)));
- } else if (pllreg == VPLL) {
- k = k & 0xfff;
- /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 1024) * (freq / (p * (1 << s)));
- } else {
- if (s < 1)
- s = 1;
- /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
- fout = m * (freq / (p * (1 << (s - 1))));
- }
+ fout = exynos_get_pll_clk(pllreg, r, k);
/* According to the user manual, in EVT1 MPLL and BPLL always gives
* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
return aclk_66;
}
+int exynos5_set_epll_clk(unsigned long rate)
+{
+ unsigned int epll_con, epll_con_k;
+ unsigned int i;
+ unsigned int lockcnt;
+ unsigned int start;
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ epll_con = readl(&clk->epll_con0);
+ epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
+ EPLL_CON0_LOCK_DET_EN_SHIFT) |
+ EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
+ EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
+ EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
+
+ for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
+ if (exynos5_epll_div[i].freq_out == rate)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(exynos5_epll_div))
+ return -1;
+
+ epll_con_k = exynos5_epll_div[i].k_dsm << 0;
+ epll_con |= exynos5_epll_div[i].en_lock_det <<
+ EPLL_CON0_LOCK_DET_EN_SHIFT;
+ epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
+ epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
+ epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
+
+ /*
+ * Required period ( in cycles) to genarate a stable clock output.
+ * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
+ * frequency input (as per spec)
+ */
+ lockcnt = 3000 * exynos5_epll_div[i].p_div;
+
+ writel(lockcnt, &clk->epll_lock);
+ writel(epll_con, &clk->epll_con0);
+ writel(epll_con_k, &clk->epll_con1);
+
+ start = get_timer(0);
+
+ while (!(readl(&clk->epll_con0) &
+ (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
+ if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
+ debug("%s: Timeout waiting for EPLL lock\n", __func__);
+ return -1;
+ }
+ }
+ return 0;
+}
+
+void exynos5_set_i2s_clk_source(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
+ (CLK_SRC_SCLK_EPLL));
+}
+
+int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
+ unsigned int dst_frq)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int div;
+
+ if ((dst_frq == 0) || (src_frq == 0)) {
+ debug("%s: Invalid requency input for prescaler\n", __func__);
+ debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+ return -1;
+ }
+
+ div = (src_frq / dst_frq);
+ if (div > AUDIO_1_RATIO_MASK) {
+ debug("%s: Frequency ratio is out of range\n", __func__);
+ debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+ return -1;
+ }
+ clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
+ (div & AUDIO_1_RATIO_MASK));
+ return 0;
+}
+
+/**
+ * Linearly searches for the most accurate main and fine stage clock scalars
+ * (divisors) for a specified target frequency and scalar bit sizes by checking
+ * all multiples of main_scalar_bits values. Will always return scalars up to or
+ * slower than target.
+ *
+ * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
+ * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
+ * @param input_freq Clock frequency to be scaled in Hz
+ * @param target_freq Desired clock frequency in Hz
+ * @param best_fine_scalar Pointer to store the fine stage divisor
+ *
+ * @return best_main_scalar Main scalar for desired frequency or -1 if none
+ * found
+ */
+static int clock_calc_best_scalar(unsigned int main_scaler_bits,
+ unsigned int fine_scalar_bits, unsigned int input_rate,
+ unsigned int target_rate, unsigned int *best_fine_scalar)
+{
+ int i;
+ int best_main_scalar = -1;
+ unsigned int best_error = target_rate;
+ const unsigned int cap = (1 << fine_scalar_bits) - 1;
+ const unsigned int loops = 1 << main_scaler_bits;
+
+ debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
+ target_rate, cap);
+
+ assert(best_fine_scalar != NULL);
+ assert(main_scaler_bits <= fine_scalar_bits);
+
+ *best_fine_scalar = 1;
+
+ if (input_rate == 0 || target_rate == 0)
+ return -1;
+
+ if (target_rate >= input_rate)
+ return 1;
+
+ for (i = 1; i <= loops; i++) {
+ const unsigned int effective_div = max(min(input_rate / i /
+ target_rate, cap), 1);
+ const unsigned int effective_rate = input_rate / i /
+ effective_div;
+ const int error = target_rate - effective_rate;
+
+ debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
+ effective_rate, error);
+
+ if (error >= 0 && error <= best_error) {
+ best_error = error;
+ best_main_scalar = i;
+ *best_fine_scalar = effective_div;
+ }
+ }
+
+ return best_main_scalar;
+}
+
+static int exynos5_set_spi_clk(enum periph_id periph_id,
+ unsigned int rate)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ int main;
+ unsigned int fine;
+ unsigned shift, pre_shift;
+ unsigned mask = 0xff;
+ u32 *reg;
+
+ main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
+ if (main < 0) {
+ debug("%s: Cannot set clock rate for periph %d",
+ __func__, periph_id);
+ return -1;
+ }
+ main = main - 1;
+ fine = fine - 1;
+
+ switch (periph_id) {
+ case PERIPH_ID_SPI0:
+ reg = &clk->div_peric1;
+ shift = 0;
+ pre_shift = 8;
+ break;
+ case PERIPH_ID_SPI1:
+ reg = &clk->div_peric1;
+ shift = 16;
+ pre_shift = 24;
+ break;
+ case PERIPH_ID_SPI2:
+ reg = &clk->div_peric2;
+ shift = 0;
+ pre_shift = 8;
+ break;
+ case PERIPH_ID_SPI3:
+ reg = &clk->sclk_div_isp;
+ shift = 0;
+ pre_shift = 4;
+ break;
+ case PERIPH_ID_SPI4:
+ reg = &clk->sclk_div_isp;
+ shift = 12;
+ pre_shift = 16;
+ break;
+ default:
+ debug("%s: Unsupported peripheral ID %d\n", __func__,
+ periph_id);
+ return -1;
+ }
+ clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
+ clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
+
+ return 0;
++
+ static unsigned long exynos4_get_i2c_clk(void)
+ {
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long sclk, aclk_100;
+ unsigned int ratio;
+
+ sclk = get_pll_clk(APLL);
+
+ ratio = (readl(&clk->div_top)) >> 4;
+ ratio &= 0xf;
+ aclk_100 = sclk / (ratio + 1);
+ return aclk_100;
}
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
return exynos5_get_i2c_clk();
+ } else if (cpu_is_exynos4()) {
+ return exynos4_get_i2c_clk();
} else {
debug("I2C clock is not set for this CPU\n");
return 0;
if (cpu_is_exynos4())
exynos4_set_mipi_clk();
}
+
+int set_spi_clk(int periph_id, unsigned int rate)
+{
+ if (cpu_is_exynos5())
+ return exynos5_set_spi_clk(periph_id, rate);
+ else
+ return 0;
+}
+
+int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
+{
+
+ if (cpu_is_exynos5())
+ return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq);
+ else
+ return 0;
+}
+
+void set_i2s_clk_source(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_i2s_clk_source();
+}
+
+int set_epll_clk(unsigned long rate)
+{
+ if (cpu_is_exynos5())
+ return exynos5_set_epll_clk(rate);
+ else
+ return 0;
+}
s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
}
+
return 0;
}
}
}
+static void exynos5_i2s_config(int peripheral)
+{
+ int i;
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ for (i = 0; i < 5; i++)
+ s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+}
+
+void exynos5_spi_config(int peripheral)
+{
+ int cfg = 0, pin = 0, i;
+ struct s5p_gpio_bank *bank = NULL;
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+ struct exynos5_gpio_part2 *gpio2 =
+ (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
+
+ switch (peripheral) {
+ case PERIPH_ID_SPI0:
+ bank = &gpio1->a2;
+ cfg = GPIO_FUNC(0x2);
+ pin = 0;
+ break;
+ case PERIPH_ID_SPI1:
+ bank = &gpio1->a2;
+ cfg = GPIO_FUNC(0x2);
+ pin = 4;
+ break;
+ case PERIPH_ID_SPI2:
+ bank = &gpio1->b1;
+ cfg = GPIO_FUNC(0x5);
+ pin = 1;
+ break;
+ case PERIPH_ID_SPI3:
+ bank = &gpio2->f1;
+ cfg = GPIO_FUNC(0x2);
+ pin = 0;
+ break;
+ case PERIPH_ID_SPI4:
+ for (i = 0; i < 2; i++) {
+ s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+ }
+ break;
+ }
+ if (peripheral != PERIPH_ID_SPI4) {
+ for (i = pin; i < pin + 4; i++)
+ s5p_gpio_cfg_pin(bank, i, cfg);
+ }
+}
+
static int exynos5_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
case PERIPH_ID_I2C7:
exynos5_i2c_config(peripheral, flags);
break;
+ case PERIPH_ID_I2S1:
+ exynos5_i2s_config(peripheral);
+ break;
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ exynos5_spi_config(peripheral);
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int exynos4_mmc_config(int peripheral, int flags)
+{
+ struct exynos4_gpio_part2 *gpio2 =
+ (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+ struct s5p_gpio_bank *bank, *bank_ext;
+ int i;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ bank = &gpio2->k0;
+ bank_ext = &gpio2->k1;
+ break;
+ case PERIPH_ID_SDMMC2:
+ bank = &gpio2->k2;
+ bank_ext = &gpio2->k3;
+ break;
+ default:
+ return -1;
+ }
+ for (i = 0; i < 7; i++) {
+ if (i == 2)
+ continue;
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ }
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = 3; i < 7; i++) {
+ s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
+ s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
+ s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ }
+ }
+
+ return 0;
+}
+
+static int exynos4_pinmux_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC2:
+ return exynos4_mmc_config(peripheral, flags);
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC3:
+ case PERIPH_ID_SDMMC4:
+ printf("SDMMC device %d not implemented\n", peripheral);
+ return -1;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
return 0;
}
+ static void exynos4_i2c_config(int peripheral, int flags)
+ {
+ struct exynos4_gpio_part1 *gpio1 =
+ (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+ break;
+ }
+ }
+
+ static int exynos4_pinmux_config(int peripheral, int flags)
+ {
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ exynos4_i2c_config(peripheral, flags);
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+ }
+
int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5())
#define EXYNOS4_ADDR_BASE 0x10000000
/* EXYNOS4 */
+ #define EXYNOS4_I2C_SPACING 0x10000
+
#define EXYNOS4_GPIO_PART3_BASE 0x03860000
#define EXYNOS4_PRO_ID 0x10000000
#define EXYNOS4_SYSREG_BASE 0x10010000
#define EXYNOS4_UART_BASE 0x13800000
#define EXYNOS4_I2C_BASE 0x13860000
#define EXYNOS4_ADC_BASE 0x13910000
+#define EXYNOS4_SPI_BASE 0x13920000
#define EXYNOS4_PWMTIMER_BASE 0x139D0000
#define EXYNOS4_MODEM_BASE 0x13A00000
#define EXYNOS4_USBPHY_CONTROL 0x10020704
+#define EXYNOS4_I2S_BASE 0xE2100000
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5 */
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_SROMC_BASE 0x12250000
#define EXYNOS5_UART_BASE 0x12C00000
#define EXYNOS5_I2C_BASE 0x12C60000
+#define EXYNOS5_SPI_BASE 0x12D20000
+#define EXYNOS5_I2S_BASE 0x12D60000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
+#define EXYNOS5_SPI_ISP_BASE 0x131A0000
#define EXYNOS5_GPIO_PART2_BASE 0x13400000
#define EXYNOS5_FIMD_BASE 0x14400000
#define EXYNOS5_DP_BASE 0x145B0000
IS_SAMSUNG_TYPE(exynos4, 0x4)
IS_SAMSUNG_TYPE(exynos5, 0x5)
+#define IS_EXYNOS_TYPE(type, id) \
+static inline int proid_is_##type(void) \
+{ \
+ return s5p_cpu_id == id; \
+}
+
+IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos5250, 0x5250)
+
#define SAMSUNG_BASE(device, base) \
static inline unsigned int samsung_get_base_##device(void) \
{ \
SAMSUNG_BASE(sysreg, SYSREG_BASE)
SAMSUNG_BASE(fimd, FIMD_BASE)
SAMSUNG_BASE(i2c, I2C_BASE)
+SAMSUNG_BASE(i2s, I2S_BASE)
SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
SAMSUNG_BASE(usb_otg, USBOTG_BASE)
SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
SAMSUNG_BASE(power, POWER_BASE)
+SAMSUNG_BASE(spi, SPI_BASE)
+SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
#endif
#endif /* _EXYNOS4_CPU_H */
#include <asm/arch/mx35_pins.h>
#include <asm/arch/iomux.h>
#include <i2c.h>
- #include <pmic.h>
+ #include <power/pmic.h>
#include <fsl_pmic.h>
#include <mmc.h>
#include <fsl_esdhc.h>
mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
}
+static void setup_iomux_usbotg(void)
+{
+ int in_pad, out_pad;
+
+ /* Set up pins for USBOTG. */
+ mxc_request_iomux(MX35_PIN_USBOTG_PWR,
+ MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_USBOTG_OC,
+ MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+ in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+ out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+ PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+
static void setup_iomux_fec(void)
{
int pad;
__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
setup_iomux_i2c();
+ setup_iomux_usbotg();
setup_iomux_fec();
setup_iomux_spi();
static inline int pmic_detect(void)
{
unsigned int id;
- struct pmic *p = get_pmic();
+ struct pmic *p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
pmic_reg_read(p, REG_IDENTIFICATION, &id);
u8 val;
u32 pmic_val;
struct pmic *p;
+ int ret;
+
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return ret;
- pmic_init();
if (pmic_detect()) {
- p = get_pmic();
+ p = pmic_get("FSL_PMIC");
mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
MUX_CONFIG_ALT1);
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#include <asm/arch/mipi_dsim.h>
#include <asm/arch/watchdog.h>
#include <asm/arch/power.h>
- #include <pmic.h>
+ #include <power/pmic.h>
#include <usb/s3c_udc.h>
- #include <max8997_pmic.h>
+ #include <power/max8997_pmic.h>
#include <libtizen.h>
+ #include <power/max8997_muic.h>
+ #include <power/battery.h>
+ #include <power/max17042_fg.h>
#include "setup.h"
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
- #if defined(CONFIG_PMIC)
- pmic_init();
- #endif
-
return 0;
}
s5p_gpio_direction_output(&gpio2->y4, 1, 1);
}
+ static void trats_low_power_mode(void)
+ {
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ struct exynos4_power *pwr =
+ (struct exynos4_power *)samsung_get_base_power();
+
+ /* Power down CORE1 */
+ /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
+ writel(0x0, &pwr->arm_core1_configuration);
+
+ /* Change the APLL frequency */
+ /* ENABLE (1 enable) | LOCKED (1 locked) */
+ /* [31] | [29] */
+ /* FSEL | MDIV | PDIV | SDIV */
+ /* [27] | [25:16] | [13:8] | [2:0] */
+ writel(0xa0c80604, &clk->apll_con0);
+
+ /* Change CPU0 clock divider */
+ /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
+ /* [30:28] | [26:24] | [22:20] | [18:16] */
+ /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
+ /* [14:12] | [10:8] | [6:4] | [2:0] */
+ writel(0x00000100, &clk->div_cpu0);
+
+ /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
+ while (readl(&clk->div_stat_cpu0) & 0x1111111)
+ continue;
+
+ /* Change clock divider ratio for DMC */
+ /* DMCP_RATIO | DMCD_RATIO */
+ /* [22:20] | [18:16] */
+ /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
+ /* [14:12] | [10:8] | [6:4] | [2:0] */
+ writel(0x13113117, &clk->div_dmc0);
+
+ /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
+ while (readl(&clk->div_stat_dmc0) & 0x11111111)
+ continue;
+
+ /* Turn off unnecessary power domains */
+ writel(0x0, &pwr->xxti_configuration); /* XXTI */
+ writel(0x0, &pwr->cam_configuration); /* CAM */
+ writel(0x0, &pwr->tv_configuration); /* TV */
+ writel(0x0, &pwr->mfc_configuration); /* MFC */
+ writel(0x0, &pwr->g3d_configuration); /* G3D */
+ writel(0x0, &pwr->gps_configuration); /* GPS */
+ writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
+
+ /* Turn off unnecessary clocks */
+ writel(0x0, &clk->gate_ip_cam); /* CAM */
+ writel(0x0, &clk->gate_ip_tv); /* TV */
+ writel(0x0, &clk->gate_ip_mfc); /* MFC */
+ writel(0x0, &clk->gate_ip_g3d); /* G3D */
+ writel(0x0, &clk->gate_ip_image); /* IMAGE */
+ writel(0x0, &clk->gate_ip_gps); /* GPS */
+ }
+
+ static int pmic_init_max8997(void)
+ {
+ struct pmic *p = pmic_get("MAX8997_PMIC");
+ int i = 0, ret = 0;
+ u32 val;
+
+ if (pmic_probe(p))
+ return -1;
+
+ /* BUCK1 VARM: 1.2V */
+ val = (1200000 - 650000) / 25000;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
+ val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
+
+ /* BUCK2 VINT: 1.1V */
+ val = (1100000 - 650000) / 25000;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
+ val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
+
+
+ /* BUCK3 G3D: 1.1V - OFF */
+ ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
+ val &= ~ENBUCK;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
+
+ val = (1100000 - 750000) / 50000;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
+
+ /* BUCK4 CAMISP: 1.2V - OFF */
+ ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
+ val &= ~ENBUCK;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
+
+ val = (1200000 - 650000) / 25000;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
+
+ /* BUCK5 VMEM: 1.2V */
+ val = (1200000 - 650000) / 25000;
+ for (i = 0; i < 8; i++)
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
+
+ val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
+
+ /* BUCK6 CAM AF: 2.8V */
+ /* No Voltage Setting Register */
+ /* GNSLCT 3.0X */
+ val = GNSLCT;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
+
+ /* BUCK7 VCC_SUB: 2.0V */
+ val = (2000000 - 750000) / 50000;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
+
+ /* LDO1 VADC: 3.3V */
+ val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
+
+ /* LDO1 Disable active discharging */
+ ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
+ val &= ~LDO_ADE;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
+
+ /* LDO2 VALIVE: 1.1V */
+ val = max8997_reg_ldo(1100000) | EN_LDO;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
+
+ /* LDO3 VUSB/MIPI: 1.1V */
+ val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
+
+ /* LDO4 VMIPI: 1.8V */
+ val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
+
+ /* LDO5 VHSIC: 1.2V */
+ val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
+
+ /* LDO6 VCC_1.8V_PDA: 1.8V */
+ val = max8997_reg_ldo(1800000) | EN_LDO;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
+
+ /* LDO7 CAM_ISP: 1.8V */
+ val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
+
+ /* LDO8 VDAC/VUSB: 3.3V */
+ val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
+
+ /* LDO9 VCC_2.8V_PDA: 2.8V */
+ val = max8997_reg_ldo(2800000) | EN_LDO;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
+
+ /* LDO10 VPLL: 1.1V */
+ val = max8997_reg_ldo(1100000) | EN_LDO;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
+
+ /* LDO11 TOUCH: 2.8V */
+ val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
+
+ /* LDO12 VTCAM: 1.8V */
+ val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
+
+ /* LDO13 VCC_3.0_LCD: 3.0V */
+ val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
+
+ /* LDO14 MOTOR: 3.0V */
+ val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
+
+ /* LDO15 LED_A: 2.8V */
+ val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
+
+ /* LDO16 CAM_SENSOR: 1.8V */
+ val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
+
+ /* LDO17 VTF: 2.8V */
+ val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
+
+ /* LDO18 TOUCH_LED 3.3V */
+ val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
+
+ /* LDO21 VDDQ: 1.2V */
+ val = max8997_reg_ldo(1200000) | EN_LDO;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
+
+ /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
+ val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
+ ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
+ ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
+
+ if (ret) {
+ puts("MAX8997 PMIC setting error!\n");
+ return -1;
+ }
+ return 0;
+ }
+
+ int power_init_board(void)
+ {
+ int chrg, ret;
+ struct power_battery *pb;
+ struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
+
+ ret = pmic_init(I2C_5);
+ ret |= pmic_init_max8997();
+ ret |= power_fg_init(I2C_9);
+ ret |= power_muic_init(I2C_5);
+ ret |= power_bat_init(0);
+ if (ret)
+ return ret;
+
+ p_fg = pmic_get("MAX17042_FG");
+ if (!p_fg) {
+ puts("MAX17042_FG: Not found\n");
+ return -ENODEV;
+ }
+
+ p_chrg = pmic_get("MAX8997_PMIC");
+ if (!p_chrg) {
+ puts("MAX8997_PMIC: Not found\n");
+ return -ENODEV;
+ }
+
+ p_muic = pmic_get("MAX8997_MUIC");
+ if (!p_muic) {
+ puts("MAX8997_MUIC: Not found\n");
+ return -ENODEV;
+ }
+
+ p_bat = pmic_get("BAT_TRATS");
+ if (!p_bat) {
+ puts("BAT_TRATS: Not found\n");
+ return -ENODEV;
+ }
+
+ p_fg->parent = p_bat;
+ p_chrg->parent = p_bat;
+ p_muic->parent = p_bat;
+
+ p_bat->low_power_mode = trats_low_power_mode;
+ p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
+
+ pb = p_bat->pbat;
+ chrg = p_muic->chrg->chrg_type(p_muic);
+ debug("CHARGER TYPE: %d\n", chrg);
+
+ if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
+ puts("No battery detected\n");
+ return -1;
+ }
+
+ p_fg->fg->fg_battery_check(p_fg, p_bat);
+
+ if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
+ puts("CHARGE Battery !\n");
+
+ return 0;
+ }
+
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
return 0;
}
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
}
static unsigned int get_hw_revision(void)
{
struct exynos4_gpio_part2 *gpio =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
- int i, err;
+ int err;
/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
s5p_gpio_direction_output(&gpio->k0, 2, 1);
s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
- /*
- * eMMC GPIO:
- * SDR 8-bit@48MHz at MMC0
- * GPK0[0] SD_0_CLK(2)
- * GPK0[1] SD_0_CMD(2)
- * GPK0[2] SD_0_CDn -> Not used
- * GPK0[3:6] SD_0_DATA[0:3](2)
- * GPK1[3:6] SD_0_DATA[0:3](3)
- *
- * DDR 4-bit@26MHz at MMC4
- * GPK0[0] SD_4_CLK(3)
- * GPK0[1] SD_4_CMD(3)
- * GPK0[2] SD_4_CDn -> Not used
- * GPK0[3:6] SD_4_DATA[0:3](3)
- * GPK1[3:6] SD_4_DATA[4:7](4)
- */
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK0[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
- /* GPK0[0:6] pull disable */
- s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
- /* GPK0[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
- }
-
- for (i = 3; i < 7; i++) {
- /* GPK1[3:6] special function 3 */
- s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
- /* GPK1[3:6] pull disable */
- s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
- /* GPK1[3:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
- }
-
/*
* MMC device init
* mmc0 : eMMC (8-bit buswidth)
* mmc2 : SD card (4-bit buswidth)
*/
- err = s5p_mmc_init(0, 8);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+ if (err)
+ debug("SDMMC0 not configured\n");
+ else
+ err = s5p_mmc_init(0, 8);
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
* GPX3[4] T-flash detect pin
*/
if (!s5p_gpio_get_value(&gpio->x3, 4)) {
- /*
- * SD card GPIO:
- * GPK2[0] SD_2_CLK(2)
- * GPK2[1] SD_2_CMD(2)
- * GPK2[2] SD_2_CDn -> Not used
- * GPK2[3:6] SD_2_DATA[0:3](2)
- */
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
- /* GPK2[0:6] pull disable */
- s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
- /* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
- }
- err = s5p_mmc_init(2, 4);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ if (err)
+ debug("SDMMC2 not configured\n");
+ else
+ err = s5p_mmc_init(2, 4);
}
return err;
{
int ret = 0;
u32 val = 0;
- struct pmic *p = get_pmic();
+ struct pmic *p = pmic_get("MAX8997_PMIC");
+ if (!p)
+ return -ENODEV;
if (pmic_probe(p))
return -1;
writel(0, (unsigned int)&pwr->lcd1_configuration);
writel(0, (unsigned int)&pwr->gps_configuration);
writel(0, (unsigned int)&pwr->gps_alive_configuration);
+
+ /* It is necessary to power down core 1 */
+ /* to successfully boot CPU1 in kernel */
+ writel(0, (unsigned int)&pwr->arm_core1_configuration);
}
static void board_uart_init(void)
static int lcd_power(void)
{
int ret = 0;
- struct pmic *p = get_pmic();
+ struct pmic *p = pmic_get("MAX8997_PMIC");
+ if (!p)
+ return -ENODEV;
if (pmic_probe(p))
return 0;
static int mipi_power(void)
{
int ret = 0;
- struct pmic *p = get_pmic();
+ struct pmic *p = pmic_get("MAX8997_PMIC");
+ if (!p)
+ return -ENODEV;
if (pmic_probe(p))
return 0;
*/
#include <common.h>
+#include <spi.h>
+#include <lcd.h>
#include <asm/io.h>
+#include <asm/gpio.h>
#include <asm/arch/adc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <pmic.h>
+#include <usb/s3c_udc.h>
+#include <asm/arch/cpu.h>
+#include <max8998_pmic.h>
+#include <asm/arch/watchdog.h>
+#include <libtizen.h>
+#include <ld9040.h>
+ #include <power/pmic.h>
+ #include <usb/s3c_udc.h>
+ #include <asm/arch/cpu.h>
+ #include <power/max8998_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
static void check_hw_revision(void);
+ int board_init(void)
+ {
+ gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+ gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
+
+ gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ check_hw_revision();
+ printf("HW Revision:\t0x%x\n", board_rev);
+
+ return 0;
+ }
+
+ int power_init_board(void)
+ {
+ int ret;
+
+ ret = pmic_init(I2C_5);
+ if (ret)
+ return ret;
+
+ return 0;
+ }
+
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
static int adc_power_control(int on)
{
int ret;
- struct pmic *p = get_pmic();
+ struct pmic *p = pmic_get("MAX8998_PMIC");
+ if (!p)
+ return -ENODEV;
if (pmic_probe(p))
return -1;
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- int i, err;
+ int err;
switch (get_hwrev()) {
case 0:
}
/*
- * eMMC GPIO:
- * SDR 8-bit@48MHz at MMC0
- * GPK0[0] SD_0_CLK(2)
- * GPK0[1] SD_0_CMD(2)
- * GPK0[2] SD_0_CDn -> Not used
- * GPK0[3:6] SD_0_DATA[0:3](2)
- * GPK1[3:6] SD_0_DATA[0:3](3)
- *
- * DDR 4-bit@26MHz at MMC4
- * GPK0[0] SD_4_CLK(3)
- * GPK0[1] SD_4_CMD(3)
- * GPK0[2] SD_4_CDn -> Not used
- * GPK0[3:6] SD_4_DATA[0:3](3)
- * GPK1[3:6] SD_4_DATA[4:7](4)
+ * MMC device init
+ * mmc0 : eMMC (8-bit buswidth)
+ * mmc2 : SD card (4-bit buswidth)
*/
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK0[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2);
- /* GPK0[0:6] pull disable */
- s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
- /* GPK0[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
- }
-
- for (i = 3; i < 7; i++) {
- /* GPK1[3:6] special function 3 */
- s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3);
- /* GPK1[3:6] pull disable */
- s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
- /* GPK1[3:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
- }
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+ if (err)
+ debug("SDMMC0 not configured\n");
+ else
+ err = s5p_mmc_init(0, 8);
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
- /*
- * MMC device init
- * mmc0 : eMMC (8-bit buswidth)
- * mmc2 : SD card (4-bit buswidth)
- */
- err = s5p_mmc_init(0, 8);
-
/*
* Check the T-flash detect pin
* GPX3[4] T-flash detect pin
*/
if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
- /*
- * SD card GPIO:
- * GPK2[0] SD_2_CLK(2)
- * GPK2[1] SD_2_CMD(2)
- * GPK2[2] SD_2_CDn -> Not used
- * GPK2[3:6] SD_2_DATA[0:3](2)
- */
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2);
- /* GPK2[0:6] pull disable */
- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
- /* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
- }
- err = s5p_mmc_init(2, 4);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ if (err)
+ debug("SDMMC2 not configured\n");
+ else
+ err = s5p_mmc_init(2, 4);
}
return err;
static int s5pc210_phy_control(int on)
{
int ret = 0;
- struct pmic *p = get_pmic();
+ struct pmic *p = pmic_get("MAX8998_PMIC");
+ if (!p)
+ return -ENODEV;
if (pmic_probe(p))
return -1;
.usb_flags = PHY0_SLEEP,
};
#endif
+
+int board_early_init_f(void)
+{
+ wdt_stop();
+
+ return 0;
+}
+
+#ifdef CONFIG_SOFT_SPI
+static void soft_spi_init(void)
+{
+ gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK,
+ CONFIG_SOFT_SPI_MODE & SPI_CPOL);
+ gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);
+ gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO);
+ gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS,
+ !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+ !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+ SPI_SCL(1);
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+ CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+ !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void universal_spi_scl(int bit)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit);
+}
+
+void universal_spi_sda(int bit)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit);
+}
+
+int universal_spi_read(void)
+{
+ return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO);
+}
+#endif
+
+static void init_pmic_lcd(void)
+{
+ unsigned char val;
+ int ret = 0;
+
+ struct pmic *p = get_pmic();
+
+ if (pmic_probe(p))
+ return;
+
+ /* LDO7 1.8V */
+ val = 0x02; /* (1800 - 1600) / 100; */
+ ret |= pmic_reg_write(p, MAX8998_REG_LDO7, val);
+
+ /* LDO17 3.0V */
+ val = 0xe; /* (3000 - 1600) / 100; */
+ ret |= pmic_reg_write(p, MAX8998_REG_LDO17, val);
+
+ /* Disable unneeded regulators */
+ /*
+ * ONOFF1
+ * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
+ * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
+ */
+ val = 0xB9;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF1, val);
+
+ /* ONOFF2
+ * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
+ * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
+ */
+ val = 0x50;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF2, val);
+
+ /* ONOFF3
+ * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
+ * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
+ */
+ val = 0x00;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF3, val);
+
+ if (ret)
+ puts("LCD pmic initialisation error!\n");
+}
+
+static void lcd_cfg_gpio(void)
+{
+ unsigned int i, f3_end = 4;
+
+ for (i = 0; i < 8; i++) {
+ /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
+ s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+ /* pull-up/down disable */
+ s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+
+ /* drive strength to max (24bit) */
+ s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+ s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
+ s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+ }
+
+ for (i = 0; i < f3_end; i++) {
+ /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
+ s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
+ /* pull-up/down disable */
+ s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+ /* drive strength to max (24bit) */
+ s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+ }
+
+ /* gpio pad configuration for LCD reset. */
+ s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
+
+ spi_init();
+}
+
+static void reset_lcd(void)
+{
+ s5p_gpio_set_value(&gpio2->y4, 5, 1);
+ udelay(10000);
+ s5p_gpio_set_value(&gpio2->y4, 5, 0);
+ udelay(10000);
+ s5p_gpio_set_value(&gpio2->y4, 5, 1);
+ udelay(100);
+}
+
+static void lcd_power_on(void)
+{
+ struct pmic *p = get_pmic();
+
+ if (pmic_probe(p))
+ return;
+
+ pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
+ pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
+}
+
+vidinfo_t panel_info = {
+ .vl_freq = 60,
+ .vl_col = 480,
+ .vl_row = 800,
+ .vl_width = 480,
+ .vl_height = 800,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+
+ .vl_bpix = 5, /* Bits per pixel */
+
+ /* LD9040 LCD Panel */
+ .vl_hspw = 2,
+ .vl_hbpd = 16,
+ .vl_hfpd = 16,
+
+ .vl_vspw = 2,
+ .vl_vbpd = 8,
+ .vl_vfpd = 8,
+ .vl_cmd_allow_len = 0xf,
+
+ .win_id = 0,
+ .cfg_gpio = lcd_cfg_gpio,
+ .backlight_on = NULL,
+ .lcd_power_on = lcd_power_on,
+ .reset_lcd = reset_lcd,
+ .dual_lcd_enabled = 0,
+
+ .init_delay = 0,
+ .power_on_delay = 10000,
+ .reset_delay = 10000,
+ .interface_mode = FIMD_RGB_INTERFACE,
+ .mipi_enabled = 0,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+ vid->logo_on = 1;
+ vid->resolution = HD_RESOLUTION;
+ vid->rgb_mode = MODE_RGB_P;
+
+#ifdef CONFIG_TIZEN
+ get_tizen_logo_info(vid);
+#endif
+
+ /* for LD9040. */
+ vid->pclk_name = 1; /* MPLL */
+ vid->sclk_div = 1;
+
+ vid->cfg_ldo = ld9040_cfg_ldo;
+ vid->enable_ldo = ld9040_enable_ldo;
+
+ setenv("lcdinfo", "lcd=ld9040");
+}
+
+int board_init(void)
+{
+ gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+ gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
+
+ gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#if defined(CONFIG_PMIC)
+ pmic_init();
+ init_pmic_lcd();
+#endif
+#ifdef CONFIG_SOFT_SPI
+ soft_spi_init();
+#endif
+ check_hw_revision();
+ printf("HW Revision:\t0x%x\n", board_rev);
+
+ return 0;
+}
imx31_litekit arm arm1136 - logicpd mx31
flea3 arm arm1136 - CarMediaLab mx35
mx35pdk arm arm1136 - freescale mx35
+woodburn arm arm1136 - - mx35
+woodburn_sd arm arm1136 woodburn - mx35 woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
rpi_b arm arm1176 rpi_b raspberrypi bcm2835
at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH
at91sam9x5ek_nandflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH
at91sam9x5ek_spiflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH
+ at91sam9x5ek_mmc arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC
at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1
at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH
M5235EVB_Flash32 m68k mcf523x m5235evb freescale - M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000
cobra5272 m68k mcf52x2 cobra5272 -
idmr m68k mcf52x2
- eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFFE00000
+ eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFF000000
eb_cpu5282_internal m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xF0000000
TASREG m68k mcf52x2 tasreg esd
M5208EVBE m68k mcf52x2 m5208evbe freescale
mpc5121ads_rev2 powerpc mpc512x mpc5121ads freescale - mpc5121ads:MPC5121ADS_REV2
cmi_mpc5xx powerpc mpc5xx cmi
PATI powerpc mpc5xx pati mpl
+ a3m071 powerpc mpc5xxx a3m071
a4m072 powerpc mpc5xxx a4m072
BC3450 powerpc mpc5xxx bc3450
canmb powerpc mpc5xxx
P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT
P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
+ P5040DS powerpc mpc85xx corenet_ds freescale
BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH
stxgp3 powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx - stxssa
gr_ep2s60 sparc leon3 - gaisler
grsim sparc leon3 - gaisler
gr_xc3s_1500 sparc leon3 - gaisler
- coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0xFC0000
+ coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0x01110000
eNET x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000
eNET_SRAM x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000
# Target ARCH CPU Board name Vendor SoC Options
COBJS-y += main.o
COBJS-y += command.o
COBJS-y += exports.o
+ COBJS-y += hash.o
COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o
COBJS-y += s_record.o
COBJS-y += xyzModem.o
COBJS-y += cmd_version.o
# environment
+ COBJS-y += env_attr.o
+ COBJS-y += env_callback.o
COBJS-y += env_common.o
+ COBJS-y += env_flags.o
COBJS-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
XCOBJS-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o
COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
COBJS-$(CONFIG_CMD_DATE) += cmd_date.o
+COBJS-$(CONFIG_CMD_SOUND) += cmd_sound.o
ifdef CONFIG_4xx
COBJS-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
endif
COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
endif
COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
+ COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
+ COBJS-$(CONFIG_CMD_HASH) += cmd_hash.o
COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o
COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o
COBJS-$(CONFIG_CMD_INI) += cmd_ini.o
COBJS-$(CONFIG_ID_EEPROM) += cmd_mac.o
COBJS-$(CONFIG_CMD_MD5SUM) += cmd_md5sum.o
COBJS-$(CONFIG_CMD_MEMORY) += cmd_mem.o
+ COBJS-$(CONFIG_CMD_IO) += cmd_io.o
COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
COBJS-$(CONFIG_MII) += miiphyutil.o
COBJS-$(CONFIG_CMD_MII) += miiphyutil.o
COBJS-y += cmd_pcmcia.o
COBJS-$(CONFIG_CMD_PORTIO) += cmd_portio.o
COBJS-$(CONFIG_CMD_PXE) += cmd_pxe.o
+ COBJS-$(CONFIG_CMD_READ) += cmd_read.o
COBJS-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o
COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o
COBJS-$(CONFIG_CMD_SATA) += cmd_sata.o
COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
COBJS-y += flash.o
COBJS-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
+ COBJS-$(CONFIG_I2C_EDID) += edid.o
COBJS-$(CONFIG_KALLSYMS) += kallsyms.o
COBJS-$(CONFIG_LCD) += lcd.o
COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
COBJS-$(CONFIG_UPDATE_TFTP) += update.o
COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
COBJS-$(CONFIG_CMD_DFU) += cmd_dfu.o
+ COBJS-$(CONFIG_CMD_GPT) += cmd_gpt.o
endif
ifdef CONFIG_SPL_BUILD
+ COBJS-y += cmd_nvedit.o
+ COBJS-y += env_common.o
+ COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += cmd_nvedit.o
+ COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_attr.o
+ COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_callback.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_common.o
+ COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_flags.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_nowhere.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
endif
# endif
#endif
+#ifndef CONFIG_LCD_ALIGNMENT
+#define CONFIG_LCD_ALIGNMENT PAGE_SIZE
+#endif
+
+/* By default we scroll by a single line */
+#ifndef CONFIG_CONSOLE_SCROLL_LINES
+#define CONFIG_CONSOLE_SCROLL_LINES 1
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
ulong lcd_setmem (ulong addr);
char lcd_is_enabled = 0;
+static char lcd_flush_dcache; /* 1 to flush dcache after each lcd update */
+
+
#ifdef NOT_USED_SO_FAR
static void lcd_getcolreg(ushort regno,
ushort *red, ushort *green, ushort *blue);
/************************************************************************/
+/* Flush LCD activity to the caches */
+void lcd_sync(void)
+{
+ /*
+ * flush_dcache_range() is declared in common.h but it seems that some
+ * architectures do not actually implement it. Is there a way to find
+ * out whether it exists? For now, ARM is safe.
+ */
+#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+ int line_length;
+
+ if (lcd_flush_dcache)
+ flush_dcache_range((u32)lcd_base,
+ (u32)(lcd_base + lcd_get_size(&line_length)));
+#endif
+}
+
+void lcd_set_flush_dcache(int flush)
+{
+ lcd_flush_dcache = (flush != 0);
+}
+
/*----------------------------------------------------------------------*/
static void console_scrollup(void)
{
- /* Copy up rows ignoring the first one */
- memcpy(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE);
+ const int rows = CONFIG_CONSOLE_SCROLL_LINES;
- /* Clear the last one */
- memset(CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE);
+ /* Copy up rows ignoring those that will be overwritten */
+ memcpy(CONSOLE_ROW_FIRST,
+ lcd_console_address + CONSOLE_ROW_SIZE * rows,
+ CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows);
+
+ /* Clear the last rows */
+ memset(lcd_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows,
+ COLOR_MASK(lcd_color_bg),
+ CONSOLE_ROW_SIZE * rows);
+
+ lcd_sync();
+ console_row -= rows;
}
/*----------------------------------------------------------------------*/
if (console_row >= CONSOLE_ROWS) {
/* Scroll everything up */
console_scrollup();
- --console_row;
+ } else {
+ lcd_sync();
}
}
while (*s) {
lcd_putc(*s++);
}
+ lcd_sync();
}
/*----------------------------------------------------------------------*/
/* ** GENERIC Initialization Routines */
/************************************************************************/
+int lcd_get_size(int *line_length)
+{
+ *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+ return *line_length * panel_info.vl_row;
+}
+
int drv_lcd_init (void)
{
struct stdio_dev lcddev;
lcd_base = (void *)(gd->fb_base);
- lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
+ lcd_get_size(&lcd_line_length);
lcd_init(lcd_base); /* LCD initialization */
}
/*----------------------------------------------------------------------*/
-static
-int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- lcd_clear();
- return 0;
-}
-
void lcd_clear(void)
{
#if LCD_BPP == LCD_MONOCHROME
console_col = 0;
console_row = 0;
+ lcd_sync();
+}
+
+static int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ lcd_clear();
+ return 0;
}
U_BOOT_CMD(
ulong lcd_setmem(ulong addr)
{
ulong size;
- int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+ int line_length;
debug("LCD panel info: %d x %d, %d bit/pix\n", panel_info.vl_col,
panel_info.vl_row, NBITS(panel_info.vl_bpix));
- size = line_length * panel_info.vl_row;
+ size = lcd_get_size(&line_length);
- /* Round up to nearest full page */
- size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+ /* Round up to nearest full page, or MMU section if defined */
+ size = ALIGN(size, CONFIG_LCD_ALIGNMENT);
+ addr = ALIGN(addr - CONFIG_LCD_ALIGNMENT + 1, CONFIG_LCD_ALIGNMENT);
/* Allocate pages for the frame buffer. */
addr -= size;
}
WATCHDOG_RESET();
+ lcd_sync();
}
#else
static inline void bitmap_plot(int x, int y) {}
}
#endif
+
+ #ifdef CONFIG_LCD_BMP_RLE8
+
+ #define BMP_RLE8_ESCAPE 0
+ #define BMP_RLE8_EOL 0
+ #define BMP_RLE8_EOBMP 1
+ #define BMP_RLE8_DELTA 2
+
+ static void draw_unencoded_bitmap(ushort **fbp, uchar *bmap, ushort *cmap,
+ int cnt)
+ {
+ while (cnt > 0) {
+ *(*fbp)++ = cmap[*bmap++];
+ cnt--;
+ }
+ }
+
+ static void draw_encoded_bitmap(ushort **fbp, ushort c, int cnt)
+ {
+ ushort *fb = *fbp;
+ int cnt_8copy = cnt >> 3;
+
+ cnt -= cnt_8copy << 3;
+ while (cnt_8copy > 0) {
+ *fb++ = c;
+ *fb++ = c;
+ *fb++ = c;
+ *fb++ = c;
+ *fb++ = c;
+ *fb++ = c;
+ *fb++ = c;
+ *fb++ = c;
+ cnt_8copy--;
+ }
+ while (cnt > 0) {
+ *fb++ = c;
+ cnt--;
+ }
+ (*fbp) = fb;
+ }
+
+ /*
+ * Do not call this function directly, must be called from
+ * lcd_display_bitmap.
+ */
+ static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb,
+ int x_off, int y_off)
+ {
+ uchar *bmap;
+ ulong width, height;
+ ulong cnt, runlen;
+ int x, y;
+ int decode = 1;
+
+ width = le32_to_cpu(bmp->header.width);
+ height = le32_to_cpu(bmp->header.height);
+ bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset);
+
+ x = 0;
+ y = height - 1;
+
+ while (decode) {
+ if (bmap[0] == BMP_RLE8_ESCAPE) {
+ switch (bmap[1]) {
+ case BMP_RLE8_EOL:
+ /* end of line */
+ bmap += 2;
+ x = 0;
+ y--;
+ /* 16bpix, 2-byte per pixel, width should *2 */
+ fb -= (width * 2 + lcd_line_length);
+ break;
+ case BMP_RLE8_EOBMP:
+ /* end of bitmap */
+ decode = 0;
+ break;
+ case BMP_RLE8_DELTA:
+ /* delta run */
+ x += bmap[2];
+ y -= bmap[3];
+ /* 16bpix, 2-byte per pixel, x should *2 */
+ fb = (uchar *) (lcd_base + (y + y_off - 1)
+ * lcd_line_length + (x + x_off) * 2);
+ bmap += 4;
+ break;
+ default:
+ /* unencoded run */
+ runlen = bmap[1];
+ bmap += 2;
+ if (y < height) {
+ if (x < width) {
+ if (x + runlen > width)
+ cnt = width - x;
+ else
+ cnt = runlen;
+ draw_unencoded_bitmap(
+ (ushort **)&fb,
+ bmap, cmap, cnt);
+ }
+ x += runlen;
+ }
+ bmap += runlen;
+ if (runlen & 1)
+ bmap++;
+ }
+ } else {
+ /* encoded run */
+ if (y < height) {
+ runlen = bmap[0];
+ if (x < width) {
+ /* aggregate the same code */
+ while (bmap[0] == 0xff &&
+ bmap[2] != BMP_RLE8_ESCAPE &&
+ bmap[1] == bmap[3]) {
+ runlen += bmap[2];
+ bmap += 2;
+ }
+ if (x + runlen > width)
+ cnt = width - x;
+ else
+ cnt = runlen;
+ draw_encoded_bitmap((ushort **)&fb,
+ cmap[bmap[1]], cnt);
+ }
+ x += runlen;
+ }
+ bmap += 2;
+ }
+ }
+ }
+ #endif
+
#if defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
#define FB_PUT_BYTE(fb, from) *(fb)++ = (255 - *(from)++)
#else
uchar *fb;
bmp_image_t *bmp=(bmp_image_t *)bmp_image;
uchar *bmap;
- ushort padded_line;
+ ushort padded_width;
unsigned long width, height, byte_width;
unsigned long pwidth = panel_info.vl_col;
unsigned colors, bpix, bmp_bpix;
}
#endif
- padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
+ padded_width = (width&0x3) ? ((width&~0x3)+4) : (width);
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
splash_align_axis(&x, pwidth, width);
switch (bmp_bpix) {
case 1: /* pass through */
case 8:
+ #ifdef CONFIG_LCD_BMP_RLE8
+ if (le32_to_cpu(bmp->header.compression) == BMP_BI_RLE8) {
+ if (bpix != 16) {
+ /* TODO implement render code for bpix != 16 */
+ printf("Error: only support 16 bpix");
+ return 1;
+ }
+ lcd_display_rle8_bitmap(bmp, cmap_base, fb, x, y);
+ break;
+ }
+ #endif
+
if (bpix != 16)
byte_width = width;
else
fb += sizeof(uint16_t) / sizeof(*fb);
}
}
- bmap += (width - padded_line);
+ bmap += (padded_width - width);
fb -= (byte_width + lcd_line_length);
}
break;
for (j = 0; j < width; j++)
fb_put_word(&fb, &bmap);
- bmap += (padded_line - width) * 2;
+ bmap += (padded_width - width) * 2;
fb -= (width * 2 + lcd_line_length);
}
break;
break;
};
+ lcd_sync();
return 0;
}
#endif
#endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */
}
+ void lcd_position_cursor(unsigned col, unsigned row)
+ {
+ console_col = min(col, CONSOLE_COLS - 1);
+ console_row = min(row, CONSOLE_ROWS - 1);
+ }
+
+ int lcd_get_pixel_width(void)
+ {
+ return panel_info.vl_col;
+ }
+
+ int lcd_get_pixel_height(void)
+ {
+ return panel_info.vl_row;
+ }
+
+ int lcd_get_screen_rows(void)
+ {
+ return CONSOLE_ROWS;
+ }
+
+ int lcd_get_screen_columns(void)
+ {
+ return CONSOLE_COLS;
+ }
+
/************************************************************************/
/************************************************************************/
#include <common.h>
#include <watchdog.h>
#include <command.h>
+ #include <fdtdec.h>
#include <malloc.h>
#include <version.h>
#ifdef CONFIG_MODEM_SUPPORT
#include <hush.h>
#endif
+ #ifdef CONFIG_OF_CONTROL
+ #include <fdtdec.h>
+ #endif
+
+ #ifdef CONFIG_OF_LIBFDT
+ #include <fdt_support.h>
+ #endif /* CONFIG_OF_LIBFDT */
+
#include <post.h>
#include <linux/ctype.h>
#include <menu.h>
- #if defined(CONFIG_SILENT_CONSOLE) || defined(CONFIG_POST) || defined(CONFIG_CMDLINE_EDITING)
DECLARE_GLOBAL_DATA_PTR;
- #endif
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
# endif /* CONFIG_AUTOBOOT_KEYED */
#endif /* CONFIG_BOOTDELAY >= 0 */
+ /*
+ * Runs the given boot command securely. Specifically:
+ * - Doesn't run the command with the shell (run_command or parse_string_outer),
+ * since that's a lot of code surface that an attacker might exploit.
+ * Because of this, we don't do any argument parsing--the secure boot command
+ * has to be a full-fledged u-boot command.
+ * - Doesn't check for keypresses before booting, since that could be a
+ * security hole; also disables Ctrl-C.
+ * - Doesn't allow the command to return.
+ *
+ * Upon any failures, this function will drop into an infinite loop after
+ * printing the error message to console.
+ */
+
+ #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) && \
+ defined(CONFIG_OF_CONTROL)
+ static void secure_boot_cmd(char *cmd)
+ {
+ cmd_tbl_t *cmdtp;
+ int rc;
+
+ if (!cmd) {
+ printf("## Error: Secure boot command not specified\n");
+ goto err;
+ }
+
+ /* Disable Ctrl-C just in case some command is used that checks it. */
+ disable_ctrlc(1);
+
+ /* Find the command directly. */
+ cmdtp = find_cmd(cmd);
+ if (!cmdtp) {
+ printf("## Error: \"%s\" not defined\n", cmd);
+ goto err;
+ }
+
+ /* Run the command, forcing no flags and faking argc and argv. */
+ rc = (cmdtp->cmd)(cmdtp, 0, 1, &cmd);
+
+ /* Shouldn't ever return from boot command. */
+ printf("## Error: \"%s\" returned (code %d)\n", cmd, rc);
+
+ err:
+ /*
+ * Not a whole lot to do here. Rebooting won't help much, since we'll
+ * just end up right back here. Just loop.
+ */
+ hang();
+ }
+
+ static void process_fdt_options(const void *blob)
+ {
+ ulong addr;
+
+ /* Add an env variable to point to a kernel payload, if available */
+ addr = fdtdec_get_config_int(gd->fdt_blob, "kernel-offset", 0);
+ if (addr)
+ setenv_addr("kernaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr));
+
+ /* Add an env variable to point to a root disk, if available */
+ addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0);
+ if (addr)
+ setenv_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr));
+ }
+ #endif /* CONFIG_OF_CONTROL */
+
+
/****************************************************************************/
void main_loop (void)
int rc = 1;
int flag;
#endif
-
+ #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) && \
+ defined(CONFIG_OF_CONTROL)
+ char *env;
+ #endif
#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
char *s;
int bootdelay;
char bcs_set[16];
#endif /* CONFIG_BOOTCOUNT_LIMIT */
+ bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
+
#ifdef CONFIG_BOOTCOUNT_LIMIT
bootcount = bootcount_load();
bootcount++;
else
#endif /* CONFIG_BOOTCOUNT_LIMIT */
s = getenv ("bootcmd");
+ #ifdef CONFIG_OF_CONTROL
+ /* Allow the fdt to override the boot command */
+ env = fdtdec_get_config_string(gd->fdt_blob, "bootcmd");
+ if (env)
+ s = env;
+
+ process_fdt_options(gd->fdt_blob);
+
+ /*
+ * If the bootsecure option was chosen, use secure_boot_cmd().
+ * Always use 'env' in this case, since bootsecure requres that the
+ * bootcmd was specified in the FDT too.
+ */
+ if (fdtdec_get_config_int(gd->fdt_blob, "bootsecure", 0))
+ secure_boot_cmd(env);
+
+ #endif /* CONFIG_OF_CONTROL */
debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
#endif /* CONFIG_MENUKEY */
#endif /* CONFIG_BOOTDELAY */
+ #if defined CONFIG_OF_CONTROL
+ set_working_fdt_addr((void *)gd->fdt_blob);
+ #endif /* CONFIG_OF_CONTROL */
+
/*
* Main Loop for Monitor Command Processing
*/
puts (tab_seq+(col&07));
col += 8 - (col&07);
} else {
- ++col; /* echo input */
- putc (c);
+ char buf[2];
+
+ /*
+ * Echo input using puts() to force am
+ * LCD flush if we are using an LCD
+ */
+ ++col;
+ buf[0] = c;
+ buf[1] = '\0';
+ puts(buf);
}
*p++ = c;
++n;
COBJS-$(CONFIG_ALI152X) += ali512x.o
COBJS-$(CONFIG_DS4510) += ds4510.o
- COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
+ COBJS-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
COBJS-$(CONFIG_NS87308) += ns87308.o
COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
+COBJS-$(CONFIG_PMIC) += pmic_core.o
+COBJS-$(CONFIG_DIALOG_PMIC) += pmic_dialog.o
+COBJS-$(CONFIG_PMIC_FSL) += pmic_fsl.o
+COBJS-$(CONFIG_PMIC_I2C) += pmic_i2c.o
+COBJS-$(CONFIG_PMIC_SPI) += pmic_spi.o
+COBJS-$(CONFIG_PMIC_MAX77686) += pmic_max77686.o
+COBJS-$(CONFIG_PMIC_MAX8998) += pmic_max8998.o
+COBJS-$(CONFIG_PMIC_MAX8997) += pmic_max8997.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+ #include <bouncebuf.h>
#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
host->reg = (struct tegra_mmc *)host->base;
}
- static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
+ static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
+ struct bounce_buffer *bbstate)
{
unsigned char ctrl;
- debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
- (u32)data->dest, data->blocks, data->blocksize);
- writel((u32)data->dest, &host->reg->sysad);
+ debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
+ bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
+ data->blocksize);
+
+ writel((u32)bbstate->bounce_buffer, &host->reg->sysad);
/*
* DMASEL[4:3]
* 00 = Selects SDMA
if (data->flags & MMC_DATA_READ)
mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
- if (data->flags & MMC_DATA_WRITE) {
- if ((uintptr_t)data->src & (ARCH_DMA_MINALIGN - 1))
- printf("Warning: unaligned write to %p may fail\n",
- data->src);
- flush_dcache_range((ulong)data->src, (ulong)data->src +
- data->blocks * data->blocksize);
- }
-
writew(mode, &host->reg->trnmod);
}
return 0;
}
- static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
+ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data, struct bounce_buffer *bbstate)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
int flags, i;
return result;
if (data)
- mmc_prepare_data(host, data);
+ mmc_prepare_data(host, data, bbstate);
debug("cmd->arg: %08x\n", cmd->cmdarg);
writel(cmd->cmdarg, &host->reg->argument);
}
}
writel(mask, &host->reg->norintsts);
- if (data->flags & MMC_DATA_READ) {
- if ((uintptr_t)data->dest & (ARCH_DMA_MINALIGN - 1))
- printf("Warning: unaligned read from %p "
- "may fail\n", data->dest);
- invalidate_dcache_range((ulong)data->dest,
- (ulong)data->dest +
- data->blocks * data->blocksize);
- }
}
udelay(1000);
return 0;
}
+ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+ {
+ void *buf;
+ unsigned int bbflags;
+ size_t len;
+ struct bounce_buffer bbstate;
+ int ret;
+
+ if (data) {
+ if (data->flags & MMC_DATA_READ) {
+ buf = data->dest;
+ bbflags = GEN_BB_WRITE;
+ } else {
+ buf = (void *)data->src;
+ bbflags = GEN_BB_READ;
+ }
+ len = data->blocks * data->blocksize;
+
+ bounce_buffer_start(&bbstate, buf, len, bbflags);
+ }
+
+ ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate);
+
+ if (data)
+ bounce_buffer_stop(&bbstate);
+
+ return ret;
+ }
+
static void mmc_change_clock(struct mmc_host *host, uint clock)
{
int div;
mmc->getcd = tegra_mmc_getcd;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ mmc->host_caps = 0;
if (bus_width == 8)
- mmc->host_caps = MMC_MODE_8BIT;
- else
- mmc->host_caps = MMC_MODE_4BIT;
+ mmc->host_caps |= MMC_MODE_8BIT;
+ if (bus_width >= 4)
+ mmc->host_caps |= MMC_MODE_4BIT;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
/*
#include <common.h>
#include <spi.h>
- #include <pmic.h>
+ #include <power/pmic.h>
#include <fsl_pmic.h>
+ #include <errno.h>
- #if defined(CONFIG_PMIC_SPI)
+#if defined(CONFIG_PMIC_FSL_MC13892)
+#define FSL_PMIC_I2C_LENGTH 3
+#elif defined(CONFIG_PMIC_FSL_MC34704)
+#define FSL_PMIC_I2C_LENGTH 1
+#endif
+
+ #if defined(CONFIG_POWER_SPI)
static u32 pmic_spi_prepare_tx(u32 reg, u32 *val, u32 write)
{
return (write << 31) | (reg << 25) | (*val & 0x00FFFFFF);
}
#endif
- int pmic_init(void)
+ int pmic_init(unsigned char bus)
{
- struct pmic *p = get_pmic();
static const char name[] = "FSL_PMIC";
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
p->name = name;
p->number_of_regs = PMIC_NUM_OF_REGS;
- #if defined(CONFIG_PMIC_SPI)
+ #if defined(CONFIG_POWER_SPI)
p->interface = PMIC_SPI;
p->bus = CONFIG_FSL_PMIC_BUS;
p->hw.spi.cs = CONFIG_FSL_PMIC_CS;
p->hw.spi.bitlen = CONFIG_FSL_PMIC_BITLEN;
p->hw.spi.flags = SPI_XFER_BEGIN | SPI_XFER_END;
p->hw.spi.prepare_tx = pmic_spi_prepare_tx;
- #elif defined(CONFIG_PMIC_I2C)
+ #elif defined(CONFIG_POWER_I2C)
p->interface = PMIC_I2C;
p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
- p->hw.i2c.tx_num = 3;
- p->bus = bus;
+ p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
+ p->bus = I2C_PMIC;
#else
- #error "You must select CONFIG_PMIC_SPI or CONFIG_PMIC_I2C"
+ #error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C"
#endif
return 0;
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o
COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
+COBJS-$(CONFIG_LD9040) += ld9040.o
COBJS-$(CONFIG_SED156X) += sed156x.o
COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
+ COBJS-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o
COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
+COBJS-$(CONFIG_VIDEO_TEGRA) += tegra.o
COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
COBJS := $(sort $(COBJS-y))
*/
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
"if tftp ${update_nand_full_filename} ; then " \
"run update_nand_get_fcb_size ; " \
"nand scrub -y 0x0 ${filesize} ; " \
- "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \
+ "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \
"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
/* PMIC Controller */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_SPI
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_SPI
+ #define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 2
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
/*
* PMIC Configs
*/
- #define CONFIG_PMIC
- #define CONFIG_PMIC_I2C
- #define CONFIG_PMIC_FSL
- #define CONFIG_PMIC_FSL_MC13892
+ #define CONFIG_POWER
+ #define CONFIG_POWER_I2C
+ #define CONFIG_POWER_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
#define CONFIG_RTC_MC13XXX
#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_CMD_DATE
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
+/* EHCI driver */
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_MXC_USB_PORT 0
+#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \
+ MXC_EHCI_POWER_PINS_ENABLED | \
+ MXC_EHCI_OC_PIN_ACTIVE_LOW)
+#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
+
/* mmc driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#endif
/* SPI PMIC */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_SPI
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_SPI
+ #define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 0
#define CONFIG_FSL_PMIC_CS (0 | 120 << 8)
#define CONFIG_FSL_PMIC_CLK 25000000
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35145
+#define CONFIG_SYS_MAIN_PWR_ON
#endif
#define CONFIG_MXC_SPI
/* PMIC Controller */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_SPI
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_SPI
+ #define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 0
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 2500000
***********************************************************/
#include <config_cmd_default.h>
-
+#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_DATE
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
/*-----------------------------------------------------------------------
* FLASH and environment organization
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC Configs */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_I2C
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_I2C
+ #define CONFIG_POWER_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
+#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_RTC_MC13XXX
/* MMC Configs */
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC Controller */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_I2C
- #define CONFIG_DIALOG_PMIC
- #define CONFIG_PMIC_FSL
- #define CONFIG_PMIC_FSL_MC13892
+ #define CONFIG_POWER
+ #define CONFIG_POWER_I2C
+ #define CONFIG_DIALOG_POWER
+ #define CONFIG_POWER_FSL
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
/* Command definition */
#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_ETHPRIME "FEC0"
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
- #define CONFIG_MMC_BOUNCE_BUFFER
+ #define CONFIG_BOUNCE_BUFFER
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#ifndef __MX6QSABRE_COMMON_CONFIG_H
#define __MX6QSABRE_COMMON_CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
- #define CONFIG_MMC_BOUNCE_BUFFER
+ #define CONFIG_BOUNCE_BUFFER
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
/* Command definition */
#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x10800000
#define CONFIG_SYS_TEXT_BASE 0x17800000
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
- #define CONFIG_MMC_BOUNCE_BUFFER
+ #define CONFIG_BOUNCE_BUFFER
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#undef CONFIG_CMD_IMLS
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_PREBOOT ""
#define CONFIG_S5P 1 /* which is in a S5P Family */
#define CONFIG_EXYNOS4210 1 /* which is in a EXYNOS4210 */
#define CONFIG_UNIVERSAL 1 /* working with Universal */
+#define CONFIG_TIZEN 1 /* TIZEN lib */
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS 7
- #define CONFIG_PMIC
- #define CONFIG_PMIC_I2C
- #define CONFIG_PMIC_MAX8998
+ #define CONFIG_POWER
+ #define CONFIG_POWER_I2C
+ #define CONFIG_POWER_MAX8998
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
+/*
+ * SPI Settings
+ */
+#define CONFIG_SOFT_SPI
+#define CONFIG_SOFT_SPI_MODE SPI_MODE_3
+#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1)
+#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3)
+#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0)
+#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3)
+
+#define SPI_DELAY udelay(1)
+#undef SPI_INIT
+#define SPI_SCL(bit) universal_spi_scl(bit)
+#define SPI_SDA(bit) universal_spi_sda(bit)
+#define SPI_READ universal_spi_read()
+#ifndef __ASSEMBLY__
+void universal_spi_scl(int bit);
+void universal_spi_sda(int bit);
+int universal_spi_read(void);
+#endif
+
+/*
+ * LCD Settings
+ */
+#define CONFIG_EXYNOS_FB
+#define CONFIG_LCD
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_32BPP
+#define CONFIG_LD9040
+#define CONFIG_EXYNOS_MIPI_DSIM
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((520 * 120 * 4) + (1 << 12))
+
#endif /* __CONFIG_H */
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
/* I2C */
#define CONFIG_TEGRA_I2C
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
+#define CONFIG_FS_EXT4
+#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_TEGRA_KEYBOARD
#define CONFIG_KEYBOARD
- #undef TEGRA_DEVICE_SETTINGS
- #define TEGRA_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
- "stdout=serial,lcd\0" \
- "stderr=serial,lcd\0"
+ /* USB keyboard */
+ #define CONFIG_USB_KEYBOARD
-#include "tegra-common-post.h"
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES 10
/* NAND support */
#define CONFIG_CMD_NAND
/* Max number of NAND devices */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* Somewhat oddly, the NAND base address must be a config option */
-#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
+#include "tegra-common-post.h"
+
#endif /* __CONFIG_H */
#undef CONFIG_CMD_IMLS
#define CONFIG_IDENT_STRING " for SMDK5250"
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SECURE_BL1_ONLY
/* U-boot copy size from boot Media to DRAM.*/
#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
+
+#define OM_STAT (0x1f << 1)
+#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
+#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
+
#define CONFIG_DOS_PARTITION
#define CONFIG_IRAM_STACK 0x02050000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_MAX_I2C_NUM 8
#define CONFIG_SYS_I2C_SLAVE 0x0
+ #define CONFIG_I2C_EDID
+/* PMIC */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_PMIC_MAX77686
+
+/* SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_EXYNOS_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define EXYNOS5_SPI_NUM_CONTROLLERS 5
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS 1
+#define CONFIG_ENV_SPI_MAX_HZ 50000000
+#endif
+
/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
#define CONFIG_SMC911X
#define CONFIG_ENV_SROM_BANK 1
#endif /*CONFIG_CMD_NET*/
+/* Enable PXE Support */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+#endif
+
+/* Sound */
+#define CONFIG_CMD_SOUND
+#ifdef CONFIG_CMD_SOUND
+#define CONFIG_SOUND
+#define CONFIG_I2S
+#define CONFIG_SOUND_WM8994
+#endif
+
/* Enable devicetree support */
#define CONFIG_OF_LIBFDT
+ /* SHA hashing */
+ #define CONFIG_CMD_HASH
+ #define CONFIG_HASH_VERIFY
+ #define CONFIG_SHA1
+ #define CONFIG_SHA256
+
#endif /* __CONFIG_H */
#else
-#ifdef CONFIG_CMD_EXT2
-#define BOOT_FSTYPE_EXT2 "ext2 "
-#else
-#define BOOT_FSTYPE_EXT2 ""
-#endif
-
-#ifdef CONFIG_CMD_FAT
-#define BOOT_FSTYPE_FAT "fat"
-#else
-#define BOOT_FSTYPE_FAT ""
-#endif
-
#ifdef CONFIG_CMD_MMC
#define BOOTCMDS_MMC \
"mmc_boot=" \
"rootpart=1\0" \
\
"script_boot=" \
- "if ${fs}load ${devtype} ${devnum}:${rootpart} " \
+ "if load ${devtype} ${devnum}:${rootpart} " \
"${scriptaddr} ${prefix}${script}; then " \
"echo ${script} found! Executing ...;" \
"source ${scriptaddr};" \
\
"scan_boot=" \
"echo Scanning ${devtype} ${devnum}...; " \
- "for fs in ${boot_fstypes}; do " \
- "for prefix in ${boot_prefixes}; do " \
- "for script in ${boot_scripts}; do " \
- "run script_boot; " \
- "done; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "for script in ${boot_scripts}; do " \
+ "run script_boot; " \
"done; " \
"done;\0" \
\
BOOT_TARGETS_DHCP " " \
"\0" \
\
- "boot_fstypes=" \
- BOOT_FSTYPE_EXT2 " " \
- BOOT_FSTYPE_FAT " " \
- "\0" \
- \
"boot_prefixes=/ /boot/\0" \
\
"boot_scripts=boot.scr.uimg boot.scr\0" \
"fdt_addr_r=0x02000000\0" \
"ramdisk_addr_r=0x02100000\0" \
- "stdout=serial\0" \
- "stderr=serial\0" \
+ #ifdef CONFIG_TEGRA_KEYBOARD
+ #define STDIN_KBD_KBC ",tegra-kbc"
+ #else
+ #define STDIN_KBD_KBC ""
+ #endif
+
+ #ifdef CONFIG_USB_KEYBOARD
+ #define STDIN_KBD_USB ",usbkbd"
+ #define CONFIG_SYS_USB_EVENT_POLL
+ #define CONFIG_PREBOOT "usb start"
+ #else
+ #define STDIN_KBD_USB ""
+ #endif
+
+ #define TEGRA_DEVICE_SETTINGS \
+ "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \
++ "stdout=serial,lcd\0" \
++ "stderr=serial,lcd\0" \
+
#define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA_DEVICE_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
#ifdef CONFIG_EFI_PARTITION
#undef CONFIG_EFI_PARTITION
#endif
+#ifdef CONFIG_CMD_FS_GENERIC
+#undef CONFIG_CMD_FS_GENERIC
+#endif
+#ifdef CONFIG_CMD_EXT4
+#undef CONFIG_CMD_EXT4
+#endif
#ifdef CONFIG_CMD_EXT2
#undef CONFIG_CMD_EXT2
#endif
#ifdef CONFIG_CMD_FAT
#undef CONFIG_CMD_FAT
#endif
+#ifdef CONFIG_FS_EXT4
+#undef CONFIG_FS_EXT4
+#endif
+#ifdef CONFIG_FS_FAT
+#undef CONFIG_FS_FAT
+#endif
/* remove USB */
#ifdef CONFIG_USB_EHCI
#include <asm/arch/tegra.h> /* get chip and board defs */
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
+
/*
* Display CPU and Board information
*/
*/
#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
#define CONFIG_EHCI_IS_TDI
- #define CONFIG_EHCI_DCACHE
/* Total I2C ports on Tegra20 */
#define TEGRA_I2C_NUM_CONTROLLERS 4
#define CONFIG_SYS_NO_FLASH
- /* Environment information, boards can override if required */
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
- #define TEGRA_DEVICE_SETTINGS "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0"
#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
+ /* Misc utility code */
+ #define CONFIG_BOUNCE_BUFFER
+
#endif /* __TEGRA20_COMMON_H */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_DFU
+ #define CONFIG_CMD_GPT
/* FAT */
#define CONFIG_CMD_FAT
#define CONFIG_BOOTBLOCK "10"
#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
+ /* Tizen - partitions definitions */
+ #define PARTS_CSA "csa-mmc"
+ #define PARTS_BOOTLOADER "u-boot"
+ #define PARTS_BOOT "boot"
+ #define PARTS_ROOT "platform"
+ #define PARTS_DATA "data"
+ #define PARTS_CSC "csc"
+ #define PARTS_UMS "ums"
+
+ #define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+ "name="PARTS_BOOTLOADER",size=60MiB," \
+ "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
+ "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+ "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+ "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+ "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
+
#define CONFIG_DFU_ALT \
"dfu_alt_info=" \
"u-boot mmc 80 400;" \
"mmcbootpart=2\0" \
"mmcrootpart=3\0" \
"opts=always_resume=1\0" \
- CONFIG_DFU_ALT
+ "partitions=" PARTS_DEFAULT \
+ CONFIG_DFU_ALT \
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HZ 1000
-/* TRATS has 2 banks of DRAM */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */
-#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */
+/* TRATS has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 4
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
#define CONFIG_DOS_PARTITION
+ /* GPT */
+ #define CONFIG_EFI_PARTITION
+ #define CONFIG_PARTITION_UUIDS
+
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
#define I2C_INIT multi_i2c_init()
- #define CONFIG_PMIC
- #define CONFIG_PMIC_I2C
- #define CONFIG_PMIC_MAX8997
+ #define CONFIG_POWER
+ #define CONFIG_POWER_I2C
+ #define CONFIG_POWER_MAX8997
+ #define CONFIG_POWER_FG
+ #define CONFIG_POWER_FG_MAX17042
+ #define CONFIG_POWER_MUIC
+ #define CONFIG_POWER_MUIC_MAX8997
+ #define CONFIG_POWER_BATTERY
+ #define CONFIG_POWER_BATTERY_TRATS
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
+#define CONFIG_FS_EXT4
+#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
+ /* USB keyboard */
+ #define CONFIG_USB_KEYBOARD
+
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_ENV_IS_IN_SPI_FLASH
/* PMIC Controller */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_SPI
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_SPI
+ #define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 0
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 2500000
/* 166 MHz DDR RAM */
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
+#define CONFIG_SYS_MAIN_PWR_ON
#define CONFIG_SYS_NO_FLASH
typedef u64 fdt_addr_t;
#define FDT_ADDR_T_NONE (-1ULL)
#define fdt_addr_to_cpu(reg) be64_to_cpu(reg)
+ #define fdt_size_to_cpu(reg) be64_to_cpu(reg)
#else
typedef u32 fdt_addr_t;
#define FDT_ADDR_T_NONE (-1U)
#define fdt_addr_to_cpu(reg) be32_to_cpu(reg)
+ #define fdt_size_to_cpu(reg) be32_to_cpu(reg)
#endif
/* Information obtained about memory from the FDT */
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
+ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
+ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
COMPAT_COUNT,
};
/* This tells us whether a fdt_gpio_state record is valid or not */
#define fdt_gpio_isvalid(x) ((x)->gpio != FDT_GPIO_NONE)
+ /**
+ * Read the GPIO taking into account the polarity of the pin.
+ *
+ * @param gpio pointer to the decoded gpio
+ * @return value of the gpio if successful, < 0 if unsuccessful
+ */
+ int fdtdec_get_gpio(struct fdt_gpio_state *gpio);
+
+ /**
+ * Write the GPIO taking into account the polarity of the pin.
+ *
+ * @param gpio pointer to the decoded gpio
+ * @return 0 if successful
+ */
+ int fdtdec_set_gpio(struct fdt_gpio_state *gpio, int val);
+
/**
* Find the next numbered alias for a peripheral. This is used to enumerate
* all the peripherals of a certain type.
int fdtdec_next_alias(const void *blob, const char *name,
enum fdt_compat_id id, int *upto);
+ /**
+ * Find the compatible ID for a given node.
+ *
+ * Generally each node has at least one compatible string attached to it.
+ * This function looks through our list of known compatible strings and
+ * returns the corresponding ID which matches the compatible string.
+ *
+ * @param blob FDT blob to use
+ * @param node Node containing compatible string to find
+ * @return compatible ID, or COMPAT_UNKNOWN if we cannot find a match
+ */
+ enum fdt_compat_id fdtdec_lookup(const void *blob, int node);
+
/**
* Find the next compatible node for a peripheral.
*
s32 fdtdec_get_int(const void *blob, int node, const char *prop_name,
s32 default_val);
+ /**
+ * Look up a 64-bit integer property in a node and return it. The property
+ * must have at least 8 bytes of data (2 cells). The first two cells are
+ * concatenated to form a 8 bytes value, where the first cell is top half and
+ * the second cell is bottom half.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @param default_val default value to return if the property is not found
+ * @return integer value, if found, or default_val if not
+ */
+ uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
+ uint64_t default_val);
+
/**
* Checks whether a node is enabled.
* This looks for a 'status' property. If this exists, then returns 1 if
int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name,
struct fdt_gpio_state *gpio);
+ /**
+ * Decode a list of GPIOs from an FDT. This creates a list of GPIOs with no
+ * terminating item.
+ *
+ * @param blob FDT blob to use
+ * @param node Node to look at
+ * @param prop_name Node property name
+ * @param gpio Array of gpio elements to fill from FDT. This will be
+ * untouched if either 0 or an error is returned
+ * @param max_count Maximum number of elements allowed
+ * @return number of GPIOs read if ok, -FDT_ERR_BADLAYOUT if max_count would
+ * be exceeded, or -FDT_ERR_NOTFOUND if the property is missing.
+ */
+ int fdtdec_decode_gpios(const void *blob, int node, const char *prop_name,
+ struct fdt_gpio_state *gpio, int max_count);
+
/**
* Set up a GPIO pin according to the provided gpio information. At present this
* just requests the GPIO.
*/
int fdtdec_setup_gpio(struct fdt_gpio_state *gpio);
+ /**
+ * Look in the FDT for a config item with the given name and return its value
+ * as a 32-bit integer. The property must have at least 4 bytes of data. The
+ * value of the first cell is returned.
+ *
+ * @param blob FDT blob to use
+ * @param prop_name Node property name
+ * @param default_val default value to return if the property is not found
+ * @return integer value, if found, or default_val if not
+ */
+ int fdtdec_get_config_int(const void *blob, const char *prop_name,
+ int default_val);
+
+ /**
+ * Look in the FDT for a config item with the given name
+ * and return whether it exists.
+ *
+ * @param blob FDT blob
+ * @param prop_name property name to look up
+ * @return 1, if it exists, or 0 if not
+ */
+ int fdtdec_get_config_bool(const void *blob, const char *prop_name);
+
+ /**
+ * Look in the FDT for a config item with the given name and return its value
+ * as a string.
+ *
+ * @param blob FDT blob
+ * @param prop_name property name to look up
+ * @returns property string, NULL on error.
+ */
+ char *fdtdec_get_config_string(const void *blob, const char *prop_name);
+
/*
* Look up a property in a node and return its contents in a byte
* array of given length. The property must have at least enough data for
*/
const u8 *fdtdec_locate_byte_array(const void *blob, int node,
const char *prop_name, int count);
+
+ /**
+ * Look up a property in a node which contains a memory region address and
+ * size. Then return a pointer to this address.
+ *
+ * The property must hold one address with a length. This is only tested on
+ * 32-bit machines.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @param ptrp returns pointer to region, or NULL if no address
+ * @param size returns size of region
+ * @return 0 if ok, -1 on error (propery not found)
+ */
+ int fdtdec_decode_region(const void *blob, int node,
+ const char *prop_name, void **ptrp, size_t *size);
#endif
extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp);
extern int bmp_display(ulong addr, int x, int y);
+/**
+ * Set whether we need to flush the dcache when changing the LCD image. This
+ * defaults to off.
+ *
+ * @param flush non-zero to flush cache after update, 0 to skip
+ */
+void lcd_set_flush_dcache(int flush);
+
#if defined CONFIG_MPC823
/*
* LCD controller stucture for MPC823 CPU
void lcd_clear(void);
int lcd_display_bitmap(ulong bmp_image, int x, int y);
+ /**
+ * Get the width of the LCD in pixels
+ *
+ * @return width of LCD in pixels
+ */
+ int lcd_get_pixel_width(void);
+
+ /**
+ * Get the height of the LCD in pixels
+ *
+ * @return height of LCD in pixels
+ */
+ int lcd_get_pixel_height(void);
+
+ /**
+ * Get the number of text lines/rows on the LCD
+ *
+ * @return number of rows
+ */
+ int lcd_get_screen_rows(void);
+
+ /**
+ * Get the number of text columns on the LCD
+ *
+ * @return number of columns
+ */
+ int lcd_get_screen_columns(void);
+
+ /**
+ * Set the position of the text cursor
+ *
+ * @param col Column to place cursor (0 = left side)
+ * @param row Row to place cursor (0 = top line)
+ */
+ void lcd_position_cursor(unsigned col, unsigned row);
+
/* Allow boards to customize the information displayed */
void lcd_show_board_info(void);
+/* Return the size of the LCD frame buffer, and the line length */
+int lcd_get_size(int *line_length);
+
/************************************************************************/
/* ** BITMAP DISPLAY SUPPORT */
/************************************************************************/
#define MAX8998_LDO3 (1 << 2)
#define MAX8998_LDO4 (1 << 1)
+#define MAX8998_LDO7 (1 << 6)
#define MAX8998_LDO8 (1 << 5)
+#define MAX8998_LDO17 (1 << 4)
#define MAX8998_SAFEOUT1 (1 << 4)
#define MAX8998_I2C_ADDR (0xCC >> 1)
COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"),
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
+ COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
+ COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
return compat_names[id];
}
- /**
- * Look in the FDT for an alias with the given name and return its node.
- *
- * @param blob FDT blob
- * @param name alias name to look up
- * @return node offset if found, or an error code < 0 otherwise
- */
- static int find_alias_node(const void *blob, const char *name)
- {
- const char *path;
- int alias_node;
-
- debug("find_alias_node: %s\n", name);
- alias_node = fdt_path_offset(blob, "/aliases");
- if (alias_node < 0)
- return alias_node;
- path = fdt_getprop(blob, alias_node, name, NULL);
- if (!path)
- return -FDT_ERR_NOTFOUND;
- return fdt_path_offset(blob, path);
- }
-
fdt_addr_t fdtdec_get_addr(const void *blob, int node,
const char *prop_name)
{
return default_val;
}
+ uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
+ uint64_t default_val)
+ {
+ const uint64_t *cell64;
+ int length;
+
+ cell64 = fdt_getprop(blob, node, prop_name, &length);
+ if (!cell64 || length < sizeof(*cell64))
+ return default_val;
+
+ return fdt64_to_cpu(*cell64);
+ }
+
int fdtdec_get_is_enabled(const void *blob, int node)
{
const char *cell;
return 1;
}
- enum fdt_compat_id fd_dec_lookup(const void *blob, int node)
+ enum fdt_compat_id fdtdec_lookup(const void *blob, int node)
{
enum fdt_compat_id id;
/* snprintf() is not available */
assert(strlen(name) < MAX_STR_LEN);
sprintf(str, "%.*s%d", MAX_STR_LEN, name, *upto);
- node = find_alias_node(blob, str);
+ node = fdt_path_offset(blob, str);
if (node < 0)
return node;
err = fdt_node_check_compatible(blob, node, compat_names[id]);
* @return number of GPIOs read if ok, -FDT_ERR_BADLAYOUT if max_count would
* be exceeded, or -FDT_ERR_NOTFOUND if the property is missing.
*/
- static int fdtdec_decode_gpios(const void *blob, int node,
- const char *prop_name, struct fdt_gpio_state *gpio,
- int max_count)
+ int fdtdec_decode_gpios(const void *blob, int node, const char *prop_name,
+ struct fdt_gpio_state *gpio, int max_count)
{
const struct fdt_property *prop;
const u32 *cell;
return err == 1 ? 0 : err;
}
+ int fdtdec_get_gpio(struct fdt_gpio_state *gpio)
+ {
+ int val;
+
+ if (!fdt_gpio_isvalid(gpio))
+ return -1;
+
+ val = gpio_get_value(gpio->gpio);
+ return gpio->flags & FDT_GPIO_ACTIVE_LOW ? val ^ 1 : val;
+ }
+
+ int fdtdec_set_gpio(struct fdt_gpio_state *gpio, int val)
+ {
+ if (!fdt_gpio_isvalid(gpio))
+ return -1;
+
+ val = gpio->flags & FDT_GPIO_ACTIVE_LOW ? val ^ 1 : val;
+ return gpio_set_value(gpio->gpio, val);
+ }
+
int fdtdec_setup_gpio(struct fdt_gpio_state *gpio)
{
/*
return NULL;
return cell;
}
+
+ int fdtdec_get_config_int(const void *blob, const char *prop_name,
+ int default_val)
+ {
+ int config_node;
+
+ debug("%s: %s\n", __func__, prop_name);
+ config_node = fdt_path_offset(blob, "/config");
+ if (config_node < 0)
+ return default_val;
+ return fdtdec_get_int(blob, config_node, prop_name, default_val);
+ }
+
+ int fdtdec_get_config_bool(const void *blob, const char *prop_name)
+ {
+ int config_node;
+ const void *prop;
+
+ debug("%s: %s\n", __func__, prop_name);
+ config_node = fdt_path_offset(blob, "/config");
+ if (config_node < 0)
+ return 0;
+ prop = fdt_get_property(blob, config_node, prop_name, NULL);
+
+ return prop != NULL;
+ }
+
+ char *fdtdec_get_config_string(const void *blob, const char *prop_name)
+ {
+ const char *nodep;
+ int nodeoffset;
+ int len;
+
+ debug("%s: %s\n", __func__, prop_name);
+ nodeoffset = fdt_path_offset(blob, "/config");
+ if (nodeoffset < 0)
+ return NULL;
+
+ nodep = fdt_getprop(blob, nodeoffset, prop_name, &len);
+ if (!nodep)
+ return NULL;
+
+ return (char *)nodep;
+ }
+
+ int fdtdec_decode_region(const void *blob, int node,
+ const char *prop_name, void **ptrp, size_t *size)
+ {
+ const fdt_addr_t *cell;
+ int len;
+
+ debug("%s: %s\n", __func__, prop_name);
+ cell = fdt_getprop(blob, node, prop_name, &len);
+ if (!cell || (len != sizeof(fdt_addr_t) * 2))
+ return -1;
+
+ *ptrp = (void *)fdt_addr_to_cpu(*cell);
+ *size = fdt_size_to_cpu(cell[1]);
+ debug("%s: size=%zx\n", __func__, *size);
+ return 0;
+ }
endif
START := $(START_PATH)/start.o
+ ifeq ($(CPU),x86)
+ START += $(START_PATH)/start16.o
+ START += $(START_PATH)/resetvec.o
+ endif
+ ifeq ($(CPU),ppc4xx)
+ START += $(START_PATH)/resetvec.o
+ endif
+ ifeq ($(CPU),mpc85xx)
+ START += $(START_PATH)/resetvec.o
+ endif
LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
+
LIBS-y += $(CPUDIR)/lib$(CPU).o
+ ifeq ($(CPU),mpc83xx)
+ LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+ endif
+ ifeq ($(CPU),mpc85xx)
+ LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+ endif
+ ifeq ($(CPU),mpc86xx)
+ LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+ endif
+
ifdef SOC
LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
endif
$(OBJTREE)/tools/mkimage -T omapimage -n byteswap \
-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
+ifneq ($(CONFIG_IMX_CONFIG),)
+$(OBJTREE)/SPL: $(obj)u-boot-spl.bin
+ $(OBJTREE)/tools/mkimage -n $(SRCTREE)/$(CONFIG_IMX_CONFIG) -T imximage \
+ -e $(CONFIG_SPL_TEXT_BASE) -d $< $@
+endif
+
ALL-y += $(obj)u-boot-spl.bin
ifdef CONFIG_SAMSUNG
projects / thirdparty / u-boot.git / commitdiff
