RISC-V: Disable uint128_t testcase of SAT_MUL when rv32

The rv32 doesn't support __uint128, and then we will have
error like below during test.

error: '__int128' is not supported on this target.

Thus, we disable the uint128_t related test when rv32.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_arith.h: Add xlen check for
	uint128_t.
	* gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c: Enable
	run test for rv64 only.
	* gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c: Ditto.
	* gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c: Ditto.
	* gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
index 3de89f47ae091ba1278ec97308fa11dbd7bfd2a0..7e2c93e5af3fbfdb4c4344290b20f9ba294061e0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
@@ -4,7 +4,9 @@
 #include <stdint-gcc.h>
 #include <stdbool.h>
 
-typedef __uint128_t uint128_t;
+#if __riscv_xlen == 64
+typedef unsigned __int128 uint128_t;
+#endif
 
 /******************************************************************************/
 /* Saturation Add (unsigned and signed)                                       */

diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
index 395a4cb060cf513f37adfa6a30d99d00d1d12356..79f62973af3d2c657304cb8e16096a067b6ca8ea 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { rv64 } } } */
 /* { dg-additional-options "-std=c99" } */
 
 #include "sat_arith.h"

diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c
index 3c8b72806a4efe77cf7ba039c6c05529281331d1..e5a94627fa00667b99d362e22c48e30d6ce7cbfc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { rv64 } } } */
 /* { dg-additional-options "-std=c99" } */
 
 #include "sat_arith.h"

diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c
index e5572de85350b8b2f0b7773588d6277fd00a6126..cbe2a221791dde56465f3445d8d6f93a3aa75b00 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { rv64 } } } */
 /* { dg-additional-options "-std=c99" } */
 
 #include "sat_arith.h"

diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c
index 2e9c39a20faaed07d0b50371a11c63232a41c8dd..1f54c303fbb2ffaae8813c076eb7594c797f4d1b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { rv64 } } } */
 /* { dg-additional-options "-std=c99" } */
 
 #include "sat_arith.h"