Allow assembler to make parallel instructions where there the seconds

(latter) outputs intersect with the first (earlier) inputs.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 124982a6eb275aaa23f7c70eb0bb551ebcba7f63..1dc872da4e2364f2dbaa06c4f1a936ce0808f4b0 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+Fri Oct 10 16:09:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * config/tc-d10v.c (parallel_ok): Allow parallel instruction issue
+       when second instruction is writing to first instructions inputs.
+       
 Mon Oct 13 15:27:17 1997  Richard Henderson  <rth@cygnus.com>
 
        * ecoff.c (PAGE_SIZE): Double to 8k as a hack to allow some C++

diff --git a/gas/config/tc-d10v.c b/gas/config/tc-d10v.c
index ec471947e99890e850e901cf76b8f27a978b9b5b..c8324b4585b1e2c2c61f859396f943fee154138b 100644 (file)
--- a/gas/config/tc-d10v.c
+++ b/gas/config/tc-d10v.c
@@ -808,15 +808,20 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
   if (exec_type == 0 && (op1->exec_type & BRANCH) != 0)
     return 0;
 
-  /* The idea here is to create two sets of bitmasks (mod and used) */
-  /* which indicate which registers are modified or used by each instruction. */
-  /* The operation can only be done in parallel if instruction 1 and instruction 2 */
-  /* modify different registers, and neither instruction modifies any registers */
-  /* the other is using.  Accesses to control registers, PSW, and memory are treated */
-  /* as accesses to a single register.  So if both instructions write memory or one */
-  /* instruction writes memory and the other reads, then they cannot be done in parallel. */
-  /* Likewise, if one instruction mucks with the psw and the other reads the PSW */
-  /* (which includes C, F0, and F1), then they cannot operate safely in parallel. */
+  /* The idea here is to create two sets of bitmasks (mod and used)
+     which indicate which registers are modified or used by each
+     instruction.  The operation can only be done in parallel if
+     instruction 1 and instruction 2 modify different registers, and
+     the first instruction does not modify registers that the second
+     is using (The second instruction can modify registers that the
+     first is using as they are only written back after the first
+     instruction has completed).  Accesses to control registers, PSW,
+     and memory are treated as accesses to a single register.  So if
+     both instructions write memory or if the first instruction writes
+     memory and the second reads, then they cannot be done in
+     parallel.  Likewise, if the first instruction mucks with the psw
+     and the second reads the PSW (which includes C, F0, and F1), then
+     they cannot operate safely in parallel. */
 
   /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
   /* r0-r15      0-15  */
@@ -898,7 +903,7 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
       else if (op->exec_type & WCAR)
        mod[j] |= 1 << 19;
     }
-  if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0 && (mod[1] & used[0]) == 0)
+  if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0)
     return 1;
   return 0;
 }