]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
cmd: zynqaes: check aes engine enabled
authorIbai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Thu, 5 Apr 2018 12:19:27 +0000 (05:19 -0700)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 23 Apr 2018 06:57:39 +0000 (08:57 +0200)
AES engine cannot be used if has not been enabled at boot time
with an encrypted boot image.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/fpga/zynqpl.c

index c3559faab2db93bc3343ac59fca7389d70ff0f6d..e9e23065491a69dee5c023b91b1dbcd43586d51f 100644 (file)
@@ -19,6 +19,7 @@
 #define DEVCFG_CTRL_PCFG_PROG_B                0x40000000
 #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK        0x00001000
 #define DEVCFG_CTRL_PCAP_RATE_EN_MASK  0x02000000
+#define DEVCFG_CTRL_PCFG_AES_EN_MASK   0x00000E00
 #define DEVCFG_ISR_FATAL_ERROR_MASK    0x00740040
 #define DEVCFG_ISR_ERROR_FLAGS_MASK    0x00340840
 #define DEVCFG_ISR_RX_FIFO_OV          0x00040000
@@ -516,6 +517,12 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
                return FPGA_FAIL;
        }
 
+       /* Check AES engine is enabled */
+       if (!(readl(&devcfg_base->ctrl) & DEVCFG_CTRL_PCFG_AES_EN_MASK)) {
+               printf("%s: AES engine is not enabled\n", __func__);
+               return FPGA_FAIL;
+       }
+
        if (zynq_dma_xfer_init(bstype)) {
                printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
                return FPGA_FAIL;