/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mpower9-vector -O2" } */
+/* Now O2 enables vectorization by default, which makes expected scalar
+ loads gone, so simply disable it. */
+/* { dg-options "-mpower9-vector -O2 -fno-tree-vectorize" } */
#ifndef TYPE
#define TYPE double
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mpower9-vector -O2" } */
+/* Now O2 enables vectorization by default, which generates unexpected float
+ conversion for vector construction, so simply disable it. */
+/* { dg-options "-mpower9-vector -O2 -fno-tree-vectorize" } */
#ifndef TYPE
#define TYPE float
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+/* Now O2 enables vectorization by default, which generates unexpected VSR
+ to GPR movement for vector construction, so simply disable it. */
+/* { dg-options "-mdejagnu-cpu=power8 -O2 -fno-tree-vectorize" } */
/* Make sure that STXSSPX is generated for float scalars in Altivec registers
on power7 instead of moving the value to a FPR register and doing a X-FORM