--- /dev/null
+;; Copyright (C) 2012-2022 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+;;
+
+;; Scheduling for ZHAOXIN lujiazui processor.
+
+;; Modeling automatons for decoders, execution pipes and AGU pipes.
+(define_automaton "lujiazui_decoder,lujiazui_core,lujiazui_agu")
+
+;; The rules for the decoder are simple:
+;; - an instruction with 1 uop can be decoded by any of the three
+;; decoders in one cycle.
+;; - an instruction with 2 uops can be decoded by decoder 0 or decoder 1
+;; but still in only one cycle.
+;; - a complex (microcode) instruction can only be decoded by
+;; decoder 0, and this takes an unspecified number of cycles.
+;;
+;; The goal is to schedule such that we have a few-one-two uops sequence
+;; in each cycle, to decode as many instructions per cycle as possible.
+(define_cpu_unit "lua_decoder0" "lujiazui_decoder")
+(define_cpu_unit "lua_decoder1" "lujiazui_decoder")
+(define_cpu_unit "lua_decoder2" "lujiazui_decoder")
+
+;; We first wish to find an instruction for lua_decoder0, so exclude
+;; lua_decoder1 and lua_decoder2 from being reserved until
+;; lua_decoder0 is reserved, and also exclude lua_decoder2
+;; from being reserved until lua_decoder1 is reserved.
+(presence_set "lua_decoder1" "lua_decoder0")
+(presence_set "lua_decoder2" "lua_decoder0")
+(presence_set "lua_decoder2" "lua_decoder1")
+
+;; Most instructions can be decoded on any of the three decoders.
+(define_reservation "lua_decodern" "lua_decoder0|lua_decoder1|lua_decoder2")
+(define_reservation "lua_decoder01" "lua_decoder0|lua_decoder1")
+
+;; The out-of-order core has six pipelines.
+;; Port 4, 5 are responsible for address calculations, load or store.
+;; Port 0, 1, 2, 3 for everything else.
+
+(define_cpu_unit "lua_p0,lua_p1,lua_p2,lua_p3" "lujiazui_core")
+(define_cpu_unit "lua_p4,lua_p5" "lujiazui_agu")
+
+(define_reservation "lua_p03" "lua_p0|lua_p3")
+(define_reservation "lua_p12" "lua_p1|lua_p2")
+(define_reservation "lua_p1p2" "lua_p1+lua_p2")
+(define_reservation "lua_p45" "lua_p4|lua_p5")
+(define_reservation "lua_p4p5" "lua_p4+lua_p5")
+(define_reservation "lua_p0p1p2p3" "lua_p0+lua_p1+lua_p2+lua_p3")
+
+;; Only the irregular instructions have to be modeled here.
+
+;; Complex instruction.
+(define_insn_reservation "lua_complex_insn" 6
+ (and (eq_attr "cpu" "lujiazui")
+ (eq_attr "type" "other,multi,str"))
+ "lua_decoder0")
+
+;; Call instruction.
+(define_insn_reservation "lua_call" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (eq_attr "type" "call,callv"))
+ "lua_decoder0,lua_p45,lua_p1")
+
+;; MOV - integer moves.
+(define_insn_reservation "lua_imov" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "imov,imovx")))
+ "lua_decodern,lua_p12")
+
+(define_insn_reservation "lua_imov_load" 4
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "imov,imovx")))
+ "lua_decoder01,lua_p45")
+
+(define_insn_reservation "lua_imov_store" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "store")
+ (eq_attr "type" "imov")))
+ "lua_decodern,lua_p12+lua_p45")
+
+(define_insn_reservation "lua_icmov" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none,unknown")
+ (eq_attr "type" "icmov")))
+ "lua_decodern,lua_p2")
+
+(define_insn_reservation "lua_icmov_load" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "icmov")))
+ "lua_decoder01,lua_p45,lua_p2")
+
+;; Push and pop.
+(define_insn_reservation "lua_push_reg" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "store")
+ (eq_attr "type" "push")))
+ "lua_decodern,lua_p12+lua_p45")
+
+(define_insn_reservation "lua_push_mem" 4
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "both")
+ (eq_attr "type" "push")))
+ "lua_decoder01,lua_p45,lua_p12+lua_p45")
+
+(define_insn_reservation "lua_pop_reg" 4
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "pop")))
+ "lua_decoder01,lua_p45")
+
+(define_insn_reservation "lua_pop_mem" 4
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "both")
+ (eq_attr "type" "pop")))
+ "lua_decoder0,lua_p45,lua_p12+lua_p45")
+
+(define_insn_reservation "lua_lea" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (eq_attr "type" "lea"))
+ "hsw_decodern,lua_p45")
+
+(define_insn_reservation "lua_shift_rotate" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none,unknown")
+ (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
+ "lua_decodern,lua_p2")
+
+(define_insn_reservation "lua_shift_rotate_load" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
+ "lua_decoder01,lua_p45,lua_p2")
+
+(define_insn_reservation "lua_shift_rotate_store" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "store")
+ (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
+ "lua_decoder01,lua_p2,lua_p45")
+
+(define_insn_reservation "lua_shift_rotate_both" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "both")
+ (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
+ "lua_decoder0,lua_p45,lua_p2,lua_p45")
+
+(define_insn_reservation "lua_branch" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "ibr")))
+ "lua_decodern,lua_p1")
+
+(define_insn_reservation "lua_indirect_branch_load" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "ibr")))
+ "lua_decodern,lua_p45,lua_p1")
+
+(define_insn_reservation "lua_leave" 4
+ (and (eq_attr "cpu" "lujiazui")
+ (eq_attr "type" "leave"))
+ "lua_decoder0,lua_p45+lua_p12,lua_p12")
+
+;; Multiplication instructions.
+
+(define_insn_reservation "lua_imul_qi" 2
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "QI")
+ (eq_attr "type" "imul,imulx"))))
+ "lua_decodern,lua_p1p2")
+
+(define_insn_reservation "lua_imul_qi_mem" 6
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "!none")
+ (and (eq_attr "mode" "QI")
+ (eq_attr "type" "imul,imulx"))))
+ "lua_decoder01,lua_p1p2+lua_p45")
+
+(define_insn_reservation "lua_imul_hisi" 3
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "HI,SI")
+ (eq_attr "type" "imul,imulx"))))
+ "lua_decoder0,lua_p1p2")
+
+(define_insn_reservation "lua_imul_hisi_mem" 7
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "!none")
+ (and (eq_attr "mode" "HI,SI")
+ (eq_attr "type" "imul,imulx"))))
+ "lua_decoder0,lua_p1p2+lua_p45")
+
+(define_insn_reservation "lua_imul_di" 12
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "DI")
+ (eq_attr "type" "imul,imulx"))))
+ "lua_decoder0,lua_p0p1p2p3")
+
+(define_insn_reservation "lua_imul_di_mem" 16
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "!none")
+ (and (eq_attr "mode" "DI")
+ (eq_attr "type" "imul,imulx"))))
+ "lua_decoder0,lua_p0p1p2p3+lua_p45")
+
+;; Division instructions.
+
+(define_insn_reservation "lua_idiv_qi" 21
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "QI")
+ (eq_attr "type" "idiv"))))
+ "lua_decoder0,lua_p0p1p2p3*21")
+
+(define_insn_reservation "lua_idiv_qi_load" 25
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "QI")
+ (eq_attr "type" "idiv"))))
+ "lua_decoder0,lua_p45,lua_p0p1p2p3*21")
+
+(define_insn_reservation "lua_idiv_hi" 22
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "HI")
+ (eq_attr "type" "idiv"))))
+ "lua_decoder0,lua_p0p1p2p3*22")
+
+(define_insn_reservation "lua_idiv_hi_load" 26
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "HI")
+ (eq_attr "type" "idiv"))))
+ "lua_decoder0,lua_p45,lua_p0p1p2p3*22")
+
+(define_insn_reservation "lua_idiv_si" 20
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "SI")
+ (eq_attr "type" "idiv"))))
+ "lua_decoder0,lua_p0p1p2p3*20")
+
+(define_insn_reservation "lua_idiv_si_load" 24
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "SI")
+ (eq_attr "type" "idiv"))))
+ "lua_decoder0,lua_p45,lua_p0p1p2p3*20")
+
+(define_insn_reservation "lua_idiv_di" 150
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "DI")
+ (eq_attr "type" "idiv"))))
+ "lua_decoder0,lua_p0p1p2p3*150")
+
+(define_insn_reservation "lua_idiv_di_load" 154
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "DI")
+ (eq_attr "type" "idiv"))))
+ "lua_decoder0,lua_p45,lua_p0p1p2p3*150")
+
+;; x87 floating point operations.
+
+(define_insn_reservation "lua_fxch" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (eq_attr "type" "fxch"))
+ "lua_decodern,lua_p1")
+
+(define_insn_reservation "lua_fop" 3
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none,unknown")
+ (eq_attr "type" "fop")))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_fop_load" 7
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "fop")))
+ "lua_decoder01,lua_p45,lua_p0")
+
+(define_insn_reservation "lua_fop_store" 3
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "store")
+ (eq_attr "type" "fop")))
+ "lua_decodern,lua_p0,lua_p45")
+
+(define_insn_reservation "lua_fop_both" 7
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "both")
+ (eq_attr "type" "fop")))
+ "lua_decoder0,lua_p45,lua_p0,lua_p45")
+
+(define_insn_reservation "lua_fsgn" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (eq_attr "type" "fsgn"))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_fistp" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "fistp")))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_fistp_mem" 4
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "!none")
+ (eq_attr "type" "fistp")))
+ "lua_decoder0,lua_p0+lua_p45")
+
+(define_insn_reservation "lua_fcmov" 3
+ (and (eq_attr "cpu" "lujiazui")
+ (eq_attr "type" "fcmov"))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_fcmp" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "fcmp")))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_fcmp_load" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "fcmp")))
+ "lua_decoder01,lua_p45,lua_p0")
+
+(define_insn_reservation "lua_fmov" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "fmov")))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_fmov_load" 4
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "!XF")
+ (eq_attr "type" "fmov"))))
+ "lua_decoder01,lua_p45,lua_p0")
+
+(define_insn_reservation "lua_fmov_XF_load" 3
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "XF")
+ (eq_attr "type" "fmov"))))
+ "lua_decoder0,lua_p45,lua_p0")
+
+(define_insn_reservation "lua_fmov_store" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "store")
+ (and (eq_attr "mode" "!XF")
+ (eq_attr "type" "fmov"))))
+ "lua_decoder0,lua_p0,lua_p45")
+
+(define_insn_reservation "lua_fmov_XF_store" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "store")
+ (and (eq_attr "mode" "XF")
+ (eq_attr "type" "fmov"))))
+ "lua_decoder0,lua_p0,lua_p45")
+
+(define_insn_reservation "lua_fmul" 4
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "fmul")))
+ "lua_decodern,lua_p3")
+
+(define_insn_reservation "lua_fmul_load" 8
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "fp_int_src" "false")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "fmul"))))
+ "lua_decoder01,lua_p45,lua_p3")
+
+(define_insn_reservation "lua_fimul_load" 8
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "fp_int_src" "true")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "fmul"))))
+ "lua_decoder0,lua_p45,lua_p3")
+
+;; fdiv instructions.
+
+(define_insn_reservation "lua_fdiv_SF" 15
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "SF")
+ (eq_attr "type" "fdiv,fpspc"))))
+ "lua_decodern,lua_p0*15")
+
+(define_insn_reservation "lua_fdiv_SF_load" 19
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "SF")
+ (eq_attr "type" "fdiv,fpspc"))))
+ "lua_decoder01,lua_p45,lua_p0*15")
+
+(define_insn_reservation "lua_fdiv_DF" 18
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "DF")
+ (eq_attr "type" "fdiv,fpspc"))))
+ "lua_decodern,lua_p0*18")
+
+(define_insn_reservation "lua_fdiv_DF_load" 22
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "DF")
+ (eq_attr "type" "fdiv,fpspc"))))
+ "lua_decoder01,lua_p45,lua_p0*18")
+
+(define_insn_reservation "lua_fdiv_XF" 22
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "XF")
+ (eq_attr "type" "fdiv,fpspc"))))
+ "lua_decoder0,lua_p0*22")
+
+(define_insn_reservation "lua_fdiv_XF_load" 26
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "XF")
+ (eq_attr "type" "fdiv,fpspc"))))
+ "lua_decoder0,lua_p45,lua_p0*22")
+
+;; MMX instructions.
+
+(define_insn_reservation "lua_mmx_sse_add_shft" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "mmxadd,sseiadd,mmxshft,sseishft")))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_mmx_sse_add_shft_load" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "mmxadd,sseiadd,mmxshft,sseishft")))
+ "lua_decoder01,lua_p45,lua_p0")
+
+(define_insn_reservation "lua_mmx_sse_add_shft_store" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "store")
+ (eq_attr "type" "mmxadd,sseiadd,mmxshft,sseishft")))
+ "lua_decodern,lua_p0,lua_p45")
+
+(define_insn_reservation "lua_mmx_mul" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "mmxmul,sseimul")))
+ "lua_decodern,lua_p3")
+
+(define_insn_reservation "lua_mmx_mul_load" 9
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "mmxmul,sseimul")))
+ "lua_decoder01,lua_p45,lua_p3")
+
+(define_insn_reservation "lua_mmxcvt" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "mmxcvt")))
+ "lua_decodern,lua_p03")
+
+(define_insn_reservation "lua_mmxcvt_load" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "mmxcvt")))
+ "lua_decoder01,lua_p45,lua_p03")
+
+;; The sfence instruction.
+(define_insn_reservation "lua_sse_sfence" 13
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "unknown")
+ (eq_attr "type" "sse")))
+ "lua_decoder0,lua_p45")
+
+(define_insn_reservation "lua_sse_SFDF" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "mode" "SF,DF")
+ (eq_attr "type" "sse")))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_sse_V4SF" 13
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "mode" "V4SF")
+ (eq_attr "type" "sse")))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_sse_V8SF" 19
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "mode" "V8SF,V4DF")
+ (eq_attr "type" "sse")))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_sse_add1" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "sseadd1")))
+ "lua_decoder0,lua_p0")
+
+(define_insn_reservation "lua_sse_add1_load" 8
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "sseadd1")))
+ "lua_decoder0,lua_p45,lua_p0")
+
+(define_insn_reservation "lua_sse_cmp" 3
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "ssecmp,ssecomi")))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_sse_cmp_load" 7
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "ssecmp,ssecomi")))
+ "lua_decoder01,lua_p45,lua_p0")
+
+(define_insn_reservation "lua_sse_logic" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "sselog,sselog1")))
+ "lua_decodern,lua_p03")
+
+(define_insn_reservation "lua_sse_logic_load" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "sselog,sselog1")))
+ "lua_decoder01,lua_p45,lua_p03")
+
+(define_insn_reservation "lua_sse_add" 3
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "sseadd")))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_sse_add_load" 7
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "sseadd")))
+ "lua_decoder01,lua_p45,lua_p0")
+
+(define_insn_reservation "lua_ssemul_ss_ps" 3
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "SF,V4SF,V8SF")
+ (eq_attr "type" "ssemul"))))
+ "lua_decodern,lua_p3")
+
+(define_insn_reservation "lua_ssemul_ss_ps_load" 7
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "SF,V4SF,V8SF")
+ (eq_attr "type" "ssemul"))))
+ "lua_decoder01,lua_p45,lua_p3")
+
+(define_insn_reservation "lua_ssemul_sd_pd" 4
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "DF,V2DF,V4DF")
+ (eq_attr "type" "ssemul"))))
+ "lua_decodern,lua_p3")
+
+(define_insn_reservation "lua_ssemul_sd_pd_load" 8
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "DF,V2DF,V4DF")
+ (eq_attr "type" "ssemul"))))
+ "lua_decoder01,lua_p45,lua_p3")
+
+(define_insn_reservation "lua_ssediv_SF" 13
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "SF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decodern,lua_p0*13")
+
+(define_insn_reservation "lua_ssediv_load_SF" 17
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "SF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decoder01,lua_p45,lua_p0*13")
+
+(define_insn_reservation "lua_ssediv_V4SF" 23
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "V4SF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decodern,lua_p0*23")
+
+(define_insn_reservation "lua_ssediv_load_V4SF" 27
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "V4SF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decoder01,lua_p45,lua_p0*23")
+
+(define_insn_reservation "lua_ssediv_V8SF" 47
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "V8SF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decoder0,lua_p0*47")
+
+(define_insn_reservation "lua_ssediv_load_V8SF" 51
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "V8SF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decoder0,lua_p45,lua_p0*47")
+
+(define_insn_reservation "lua_ssediv_SD" 17
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "DF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decodern,lua_p0*17")
+
+(define_insn_reservation "lua_ssediv_load_SD" 21
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "DF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decoder01,lua_p45,lua_p0*17")
+
+(define_insn_reservation "lua_ssediv_V2DF" 30
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "V2DF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decodern,lua_p0*30")
+
+(define_insn_reservation "lua_ssediv_load_V2DF" 34
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "V2DF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decoder01,lua_p45,lua_p0*30")
+
+(define_insn_reservation "lua_ssediv_V4DF" 56
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "V4DF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decoder0,lua_p0*56")
+
+(define_insn_reservation "lua_ssediv_load_V4DF" 60
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "V4DF")
+ (eq_attr "type" "ssediv"))))
+ "lua_decoder0,lua_p4p5,lua_p0*56")
+
+
+(define_insn_reservation "lua_sseicvt_si" 2
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "SI")
+ (and (match_operand:SF 1 "memory_operand")
+ (eq_attr "type" "sseicvt")))))
+ "lua_decoder01,lua_p0")
+
+(define_insn_reservation "lua_sseicvt_si_load" 6
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "SI")
+ (and (match_operand:SF 1 "memory_operand")
+ (eq_attr "type" "sseicvt")))))
+ "lua_decoder0,lua_p45,lua_p0")
+
+(define_insn_reservation "lua_sseicvtdf_si" 3
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "mode" "SI")
+ (and (match_operand:DF 1 "memory_operand")
+ (eq_attr "type" "sseicvt")))))
+ "lua_decodern,lua_p0")
+
+(define_insn_reservation "lua_sseicvtdf_si_load" 7
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "mode" "SI")
+ (and (match_operand:DF 1 "memory_operand")
+ (eq_attr "type" "sseicvt")))))
+ "lua_decoder01,lua_p45,lua_p0")
+
+(define_insn_reservation "lua_ssecvt" 6
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "ssecvt")))
+ "lua_decoder01,lua_p03")
+
+(define_insn_reservation "lua_ssecvt_load" 10
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "ssecvt")))
+ "lua_decoder0,lua_p45,lua_p03")
+
+(define_insn_reservation "lua_sse_mov" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "ssemov")))
+ "lua_decodern,lua_p03")
+
+(define_insn_reservation "lua_sse_mov_load" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "ssemov")))
+ "lua_decoder01,lua_p45,lua_p03")
+
+(define_insn_reservation "lua_sse_mov_store" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "store")
+ (eq_attr "type" "ssemov")))
+ "lua_decoder01,lua_p0,lua_p45")
+
+(define_insn_reservation "lua_insn_alu" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none,unknown")
+ (eq_attr "type" "alu")))
+ "lua_decodern,lua_p12")
+
+(define_insn_reservation "lua_insn_alu_load" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "alu")))
+ "lua_decoder01,lua_p45,lua_p12")
+
+(define_insn_reservation "lua_insn_alu_store" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "store")
+ (eq_attr "type" "alu")))
+ "lua_decoder01,lua_p12,lua_p45")
+
+(define_insn_reservation "lua_insn_alu_both" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "both")
+ (eq_attr "type" "alu")))
+ "lua_decoder0,lua_p45,lua_p12,lua_p45")
+
+(define_insn_reservation "lua_insn_alu1" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none,unknown")
+ (eq_attr "type" "alu1")))
+ "lua_decodern,lua_p12")
+
+(define_insn_reservation "lua_insn_alu1_load" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "alu1")))
+ "lua_decoder01,lua_p45,lua_p12")
+
+(define_insn_reservation "lua_insn_alu1_store" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "store")
+ (eq_attr "type" "alu1")))
+ "lua_decoder01,lua_p12,lua_p45")
+
+(define_insn_reservation "lua_insn_alu1_both" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "both")
+ (eq_attr "type" "alu1")))
+ "lua_decoder0,lua_p45,lua_p12,lua_p45")
+
+(define_insn_reservation "lua_insn_negnot_incdec" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "negnot,incdec")))
+ "lua_decodern,lua_p12")
+
+(define_insn_reservation "lua_insn_negnot_setcc" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "setcc")))
+ "lua_decodern,lua_p2")
+
+(define_insn_reservation "lua_insn_negnot_setcc_mem" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "!none")
+ (eq_attr "type" "negnot,setcc")))
+ "lua_decoder01,lua_p45,lua_p2,lua_p45")
+
+(define_insn_reservation "lua_insn_incdec_mem" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "!none")
+ (eq_attr "type" "incdec")))
+ "lua_decoder0,lua_p45,lua_p12,lua_p45")
+
+(define_insn_reservation "lua_insn_icmptest" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none,unknown")
+ (eq_attr "type" "icmp,test")))
+ "lua_decodern,lua_p12")
+
+(define_insn_reservation "lua_insn_icmptest_load" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "icmp,test")))
+ "lua_decoder01,lua_p45,lua_p12")
+
+(define_insn_reservation "lua_insn_icmptest_store" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "store")
+ (eq_attr "type" "icmp,test")))
+ "lua_decoder01,lua_p12,lua_p45")
+
+(define_insn_reservation "lua_insn_icmptest_both" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "both")
+ (eq_attr "type" "icmp,test")))
+ "lua_decoder0,lua_p45,lua_p12,lua_p45")
+
+(define_insn_reservation "lua_insn_sseishft1_mmx" 1
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "sseishft1,mmx,mmxcmp")))
+ "lua_decodern,lua_p03")
+
+(define_insn_reservation "lua_insn_sseishft1_mmx_mem" 5
+ (and (eq_attr "cpu" "lujiazui")
+ (and (eq_attr "memory" "load")
+ (eq_attr "type" "sseishft1,mmx,mmxcmp")))
+ "lua_decoder01,lua_p45,lua_p03")
"16", /* Func alignment. */
};
+/* lujiazui_cost should produce code tuned for ZHAOXIN lujiazui CPU. */
+static stringop_algs lujiazui_memcpy[2] = {
+ {libcall, {{32, loop, false}, {8192, rep_prefix_4_byte, false},
+ {-1, libcall, false}}},
+ {libcall, {{12, unrolled_loop, true}, {32, loop, false},
+ {6144, rep_prefix_8_byte, false},
+ {-1, libcall, false}}}};
+static stringop_algs lujiazui_memset[2] = {
+ {libcall, {{32, loop, false}, {8192, rep_prefix_4_byte, false},
+ {-1, libcall, false}}},
+ {libcall, {{12, loop, true}, {32, loop, false},
+ {640, rep_prefix_8_byte, false},
+ {-1, libcall, false}}}};
+static const
+struct processor_costs lujiazui_cost = {
+ {
+ /* Start of register allocator costs. integer->integer move cost is 2. */
+ 6, /* cost for loading QImode using movzbl. */
+ {6, 6, 6}, /* cost of loading integer registers
+ in QImode, HImode and SImode.
+ Relative to reg-reg move (2). */
+ {6, 6, 6}, /* cost of storing integer registers. */
+ 2, /* cost of reg,reg fld/fst. */
+ {6, 6, 8}, /* cost of loading fp registers
+ in SFmode, DFmode and XFmode. */
+ {6, 6, 8}, /* cost of storing fp registers
+ in SFmode, DFmode and XFmode. */
+ 2, /* cost of moving MMX register. */
+ {6, 6}, /* cost of loading MMX registers
+ in SImode and DImode. */
+ {6, 6}, /* cost of storing MMX registers
+ in SImode and DImode. */
+ 2, 3, 4, /* cost of moving XMM,YMM,ZMM register. */
+ {6, 6, 6, 10, 15}, /* cost of loading SSE registers
+ in 32,64,128,256 and 512-bit. */
+ {6, 6, 6, 10, 15}, /* cost of storing SSE registers
+ in 32,64,128,256 and 512-bit. */
+ 6, 6, /* SSE->integer and integer->SSE moves. */
+ 6, 6, /* mask->integer and integer->mask moves. */
+ {6, 6, 6}, /* cost of loading mask register
+ in QImode, HImode, SImode. */
+ {6, 6, 6}, /* cost if storing mask register
+ in QImode, HImode, SImode. */
+ 2, /* cost of moving mask register. */
+ /* End of register allocator costs. */
+ },
+
+ COSTS_N_INSNS (1), /* cost of an add instruction. */
+ COSTS_N_INSNS (1) + 1, /* cost of a lea instruction. */
+ COSTS_N_INSNS (1), /* variable shift costs. */
+ COSTS_N_INSNS (1), /* constant shift costs. */
+ {COSTS_N_INSNS (2), /* cost of starting multiply for QI. */
+ COSTS_N_INSNS (3), /* HI. */
+ COSTS_N_INSNS (3), /* SI. */
+ COSTS_N_INSNS (12), /* DI. */
+ COSTS_N_INSNS (14)}, /* other. */
+ 0, /* cost of multiply per each bit set. */
+ {COSTS_N_INSNS (22), /* cost of a divide/mod for QI. */
+ COSTS_N_INSNS (24), /* HI. */
+ COSTS_N_INSNS (24), /* SI. */
+ COSTS_N_INSNS (150), /* DI. */
+ COSTS_N_INSNS (152)}, /* other. */
+ COSTS_N_INSNS (1), /* cost of movsx. */
+ COSTS_N_INSNS (1), /* cost of movzx. */
+ 8, /* "large" insn. */
+ 17, /* MOVE_RATIO. */
+ 6, /* CLEAR_RATIO. */
+ {6, 6, 6}, /* cost of loading integer registers
+ in QImode, HImode and SImode.
+ Relative to reg-reg move (2). */
+ {6, 6, 6}, /* cost of storing integer registers. */
+ {6, 6, 6, 10, 15}, /* cost of loading SSE register
+ in 32bit, 64bit, 128bit, 256bit and 512bit. */
+ {6, 6, 6, 10, 15}, /* cost of storing SSE register
+ in 32bit, 64bit, 128bit, 256bit and 512bit. */
+ {6, 6, 6, 10, 15}, /* cost of unaligned loads. */
+ {6, 6, 6, 10, 15}, /* cost of unaligned storess. */
+ 2, 3, 4, /* cost of moving XMM,YMM,ZMM register. */
+ 6, /* cost of moving SSE register to integer. */
+ 18, 6, /* Gather load static, per_elt. */
+ 18, 6, /* Gather store static, per_elt. */
+ 32, /* size of l1 cache. */
+ 4096, /* size of l2 cache. */
+ 64, /* size of prefetch block. */
+ /* Lujiazui processor never drop prefetches, like AMD processors. */
+ 100, /* number of parallel prefetches. */
+ 3, /* Branch cost. */
+ COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
+ COSTS_N_INSNS (4), /* cost of FMUL instruction. */
+ COSTS_N_INSNS (22), /* cost of FDIV instruction. */
+ COSTS_N_INSNS (1), /* cost of FABS instruction. */
+ COSTS_N_INSNS (1), /* cost of FCHS instruction. */
+ COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
+
+ COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
+ COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */
+ COSTS_N_INSNS (3), /* cost of MULSS instruction. */
+ COSTS_N_INSNS (4), /* cost of MULSD instruction. */
+ COSTS_N_INSNS (6), /* cost of FMA SS instruction. */
+ COSTS_N_INSNS (6), /* cost of FMA SD instruction. */
+ COSTS_N_INSNS (13), /* cost of DIVSS instruction. */
+ COSTS_N_INSNS (17), /* cost of DIVSD instruction. */
+ COSTS_N_INSNS (32), /* cost of SQRTSS instruction. */
+ COSTS_N_INSNS (60), /* cost of SQRTSD instruction. */
+ 1, 4, 3, 3, /* reassoc int, fp, vec_int, vec_fp. */
+ lujiazui_memcpy,
+ lujiazui_memset,
+ COSTS_N_INSNS (4), /* cond_taken_branch_cost. */
+ COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
+ "16:11:8", /* Loop alignment. */
+ "16:11:8", /* Jump alignment. */
+ "0:0:8", /* Label alignment. */
+ "16", /* Func alignment. */
+};
+
/* Generic should produce code tuned for Core-i7 (and newer chips)
and btver1 (and newer chips). */
/* X86_TUNE_SCHEDULE: Enable scheduling. */
DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
- | m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
- | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC)
+ | m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
+ | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
on modern chips. Prefer stores affecting whole integer register
DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2
| m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
- | m_KNL | m_KNM | m_AMD_MULTIPLE | m_TREMONT | m_ALDERLAKE
- | m_GENERIC)
+ | m_KNL | m_KNM | m_AMD_MULTIPLE | m_LUJIAZUI | m_TREMONT
+ | m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
destinations to be 128bit to allow register renaming on 128bit SSE units,
that can be partly masked by careful scheduling of moves. */
DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
- | m_BDVER | m_ZNVER | m_TREMONT | m_ALDERLAKE | m_GENERIC)
+ | m_BDVER | m_ZNVER | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE
+ | m_GENERIC)
/* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids
partial write to the destination in scalar SSE conversion from FP
DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY,
"sse_partial_reg_fp_converts_dependency",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
- | m_BDVER | m_ZNVER | m_ALDERLAKE | m_GENERIC)
+ | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial
write to the destination in scalar SSE conversion from integer to FP. */
DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY,
"sse_partial_reg_converts_dependency",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
- | m_BDVER | m_ZNVER | m_ALDERLAKE | m_GENERIC)
+ | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before
several insns to break false dependency on the dest register for GLC
DEF_TUNE (X86_TUNE_MOVX, "movx",
m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
| m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL
- | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE
+ | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
| m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
| m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE
- | m_TREMONT | m_ALDERLAKE | m_GENERIC)
+ | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
conditional jump instruction for 32 bit TARGET. */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
- m_CORE_ALL | m_BDVER | m_ZNVER | m_GENERIC)
+ m_CORE_ALL | m_BDVER | m_ZNVER | m_LUJIAZUI | m_GENERIC)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
conditional jump instruction for TARGET_64BIT. */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
- | m_ZNVER | m_GENERIC)
+ | m_ZNVER | m_LUJIAZUI | m_GENERIC)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
subsequent conditional jump instruction when the condition jump
check sign flag (SF) or overflow flag (OF). */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
- | m_ZNVER | m_GENERIC)
+ | m_ZNVER | m_LUJIAZUI | m_GENERIC)
/* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
jump instruction when the alu instruction produces the CCFLAG consumed by
the conditional jump instruction. */
DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
- m_SANDYBRIDGE | m_CORE_AVX2 | m_GENERIC)
+ m_SANDYBRIDGE | m_CORE_AVX2 | m_LUJIAZUI | m_GENERIC)
/*****************************************************************************/
DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
- | m_GOLDMONT | m_GOLDMONT_PLUS | m_ATHLON_K8)
+ | m_GOLDMONT | m_GOLDMONT_PLUS | m_ATHLON_K8 | m_LUJIAZUI)
/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
considered on critical path. */
/* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits. */
DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
- m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_TREMONT
- | m_ALDERLAKE | m_GENERIC)
+ m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
+ | m_TREMONT | m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
Some chips, like 486 and Pentium works faster with separate load
and push instructions. */
DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
- | m_TREMONT | m_ALDERLAKE | m_GENERIC)
+ | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
over esp subtraction. */
/* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
on 16-bit immediate moves into memory on Core2 and Corei7. */
-DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC)
+DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_LUJIAZUI | m_GENERIC)
/* X86_TUNE_READ_MODIFY: Enable use of read-modify instructions such
as "add mem, reg". */
DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
| m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GOLDMONT
- | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC))
+ | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_LUJIAZUI
+ | m_GENERIC))
/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
for DFmode copies */
DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
- | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
- | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC))
+ | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
+ | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC))
/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
will impact LEA instruction selection. */
DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL
- | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL)
+ | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL | m_LUJIAZUI)
/* X86_TUNE_AVOID_LEA_FOR_ADDR: Avoid lea for address computation. */
DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR, "avoid_lea_for_addr",
move/set sequences of bytes with known size. */
DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB,
"prefer_known_rep_movsb_stosb",
- m_SKYLAKE | m_ALDERLAKE | m_TREMONT | m_CORE_AVX512)
+ m_SKYLAKE | m_ALDERLAKE | m_TREMONT | m_CORE_AVX512 | m_LUJIAZUI)
/* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of
compact prologues and epilogues by issuing a misaligned moves. This
FIXME: This may actualy be a win on more targets than listed here. */
DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
"misaligned_move_string_pro_epilogues",
- m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_TREMONT
+ m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_LUJIAZUI | m_TREMONT
| m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_USE_SAHF: Controls use of SAHF. */
DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
- | m_BTVER | m_ZNVER | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
- | m_ALDERLAKE | m_GENERIC)
+ | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS
+ | m_TREMONT | m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
/* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
- | m_LAKEMONT | m_AMD_MULTIPLE | m_GOLDMONT | m_GOLDMONT_PLUS
- | m_TREMONT | m_ALDERLAKE | m_GENERIC)
+ | m_LAKEMONT | m_AMD_MULTIPLE | m_LUJIAZUI | m_GOLDMONT
+ | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
for bit-manipulation instructions. */
DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi",
- m_SANDYBRIDGE | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_GENERIC)
+ m_SANDYBRIDGE | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_LUJIAZUI
+ | m_GENERIC)
/* X86_TUNE_ADJUST_UNROLL: This enables adjusting the unroll factor based
on hardware capabilities. Bdver3 hardware has a loop buffer which makes
if-converted sequence to one. */
DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
- | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC)
+ | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_LUJIAZUI | m_GENERIC)
/* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */
DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
- m_CORE_ALL | m_BDVER | m_ZNVER | m_TREMONT | m_ALDERLAKE | m_GENERIC)
+ m_CORE_ALL | m_BDVER | m_ZNVER | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE
+ | m_GENERIC)
/* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
(signed) x >> (W-1)) instead of cmove or SSE max/abs instructions. */
DEF_TUNE (X86_TUNE_EXPAND_ABS, "expand_abs",
m_CORE_ALL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT
- | m_GOLDMONT_PLUS)
+ | m_GOLDMONT_PLUS | m_LUJIAZUI)
/*****************************************************************************/
/* 387 instruction selection tuning */
DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
| m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE
- | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
- | m_GENERIC))
+ | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
+ | m_ALDERLAKE | m_GENERIC))
/* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */
-DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
+DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_LUJIAZUI)
/* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI. */
DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
- | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GOLDMONT
- | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC)
+ | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_LUJIAZUI
+ | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC)
/*****************************************************************************/
/* SSE instruction selection tuning */
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
| m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
- | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_GENERIC)
+ | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GENERIC)
/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores
instead of a sequence loading registers by parts. */
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
- | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS
- | m_TREMONT | m_ALDERLAKE | m_BDVER | m_ZNVER | m_GENERIC)
+ | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
+ | m_BDVER | m_ZNVER | m_LUJIAZUI | m_GENERIC)
/* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
precision 128bit instructions instead of double where possible. */
/* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */
DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
- m_AMD_MULTIPLE | m_CORE_ALL | m_TREMONT | m_ALDERLAKE | m_GENERIC)
+ m_AMD_MULTIPLE | m_LUJIAZUI | m_CORE_ALL | m_TREMONT | m_ALDERLAKE
+ | m_GENERIC)
/* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
xorps/xorpd and other variants. */
DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
- | m_TREMONT | m_ALDERLAKE | m_GENERIC)
+ | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_GENERIC)
/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
to SSE registers. If disabled, the moves will be done by storing
projects / thirdparty / gcc.git / commitdiff
