]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: allwinner: t527: orangepi-4a: Enable Ethernet port
authorChen-Yu Tsai <wens@csie.org>
Tue, 23 Sep 2025 14:02:46 +0000 (22:02 +0800)
committerChen-Yu Tsai <wens@csie.org>
Mon, 13 Oct 2025 07:52:14 +0000 (15:52 +0800)
On the Orangepi 4A board, the second Ethernet controller, aka the GMAC200,
is connected to an external Motorcomm YT8531 PHY. The PHY uses an external
25MHz crystal, has the SoC's PI15 pin connected to its reset pin, and
the PI16 pin for its interrupt pin.

Enable it.

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250923140247.2622602-7-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts

index 39a4e194712a285608cb0d6f67ce43a55c7b087b..9e6b21cf293ee79db6bed39188c6f52397fa9560 100644 (file)
@@ -15,6 +15,7 @@
        compatible = "xunlong,orangepi-4a", "allwinner,sun55i-t527";
 
        aliases {
+               ethernet0 = &gmac1;
                serial0 = &uart0;
        };
 
        status = "okay";
 };
 
+&gmac1 {
+       phy-mode = "rgmii-id";
+       phy-handle = <&ext_rgmii_phy>;
+       phy-supply = <&reg_cldo4>;
+
+       tx-internal-delay-ps = <0>;
+       rx-internal-delay-ps = <300>;
+
+       status = "okay";
+};
+
 &gpu {
        mali-supply = <&reg_dcdc2>;
        status = "okay";
 };
 
+&mdio1 {
+       ext_rgmii_phy: ethernet-phy@1 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <1>;
+               interrupts-extended = <&pio 8 16 IRQ_TYPE_LEVEL_LOW>; /* PI16 */
+               reset-gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
+               reset-assert-us = <10000>;
+               reset-deassert-us = <150000>;
+       };
+};
+
 &mmc0 {
        vmmc-supply = <&reg_cldo3>;
        cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */