ARM: stm32: Limit early cache enablement in SPL to STM32MP15xx

The STM32MP13xx SRAM size is half that the SRAM size on STM32MP15xx,
disable early dcache start on STM32MP13xx as the TLB itself takes
about a quarter of the SPL size. The dcache will be enabled later,
once DRAM is available and TLB can be placed in DRAM.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>

diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
index 8c09d91de0581db9e88a7502b80b5151e4c905e1..e0c6f8ba9378211e0901bde641859721c9b12247 100644 (file)
--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
@@ -28,7 +28,9 @@
  * early TLB into the .data section so that it not get cleared
  * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
  */
+#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X))
 u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
+#endif
 
 u32 get_bootmode(void)
 {
@@ -95,18 +97,19 @@ void dram_bank_mmu_setup(int bank)
  */
 static void early_enable_caches(void)
 {
+#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X))
        /* I-cache is already enabled in start.S: cpu_init_cp15 */
-
        if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
                return;
 
 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
-               gd->arch.tlb_size = PGTABLE_SIZE;
-               gd->arch.tlb_addr = (unsigned long)&early_tlb;
+       gd->arch.tlb_size = PGTABLE_SIZE;
+       gd->arch.tlb_addr = (unsigned long)&early_tlb;
 #endif
 
        /* enable MMU (default configuration) */
        dcache_enable();
+#endif
 }
 
 /*

diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c
index 9c4fafbf478ba58a08ec93d58719cf1dc579a61c..e63bdaaf42fd9c6c23307a42f178edee24da6f64 100644 (file)
--- a/arch/arm/mach-stm32mp/stm32mp1/spl.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c
@@ -220,10 +220,11 @@ void board_init_f(ulong dummy)
         * activate cache on DDR only when DDR is fully initialized
         * to avoid speculative access and issue in get_ram_size()
         */
-       if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+       if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !IS_ENABLED(CONFIG_STM32MP13X)) {
                mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
                                                CONFIG_DDR_CACHEABLE_SIZE,
                                                DCACHE_DEFAULT_OPTION);
+       }
 }
 
 void spl_board_prepare_for_boot(void)