Remove x86 cpu feature detection for tzcnt

diff --git a/arch/x86/x86_features.c b/arch/x86/x86_features.c
index d1ac51c55c799062b546cc5c91569ddafad69fdc..2c5cb54c656c95c96e6d7b31c6d14566c0745c17 100644 (file)
--- a/arch/x86/x86_features.c
+++ b/arch/x86/x86_features.c
@@ -27,7 +27,6 @@ Z_INTERNAL int x86_cpu_has_sse41;
 Z_INTERNAL int x86_cpu_has_sse42;
 Z_INTERNAL int x86_cpu_has_pclmulqdq;
 Z_INTERNAL int x86_cpu_has_vpclmulqdq;
-Z_INTERNAL int x86_cpu_has_tzcnt;
 Z_INTERNAL int x86_cpu_has_os_save_ymm;
 Z_INTERNAL int x86_cpu_has_os_save_zmm;
 
@@ -97,7 +96,6 @@ void Z_INTERNAL x86_check_features(void) {
 
         // check BMI1 bit
         // Reference: https://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf
-        x86_cpu_has_tzcnt = ebx & 0x8;
         x86_cpu_has_vpclmulqdq = ecx & 0x400;
 
         // check AVX2 bit if the OS supports saving YMM registers
@@ -116,7 +114,6 @@ void Z_INTERNAL x86_check_features(void) {
             x86_cpu_has_avx512vnni = 0;
         }
     } else {
-        x86_cpu_has_tzcnt = 0;
         x86_cpu_has_avx2 = 0;
         x86_cpu_has_avx512 = 0;
         x86_cpu_has_avx512vnni = 0;

diff --git a/arch/x86/x86_features.h b/arch/x86/x86_features.h
index 3e0d17f063303e5100fb1d77fa12ff479eeaf0b7..06677b2e12f9cafd9815fac091ee626d9b57c3d3 100644 (file)
--- a/arch/x86/x86_features.h
+++ b/arch/x86/x86_features.h
@@ -15,7 +15,6 @@ extern int x86_cpu_has_sse41;
 extern int x86_cpu_has_sse42;
 extern int x86_cpu_has_pclmulqdq;
 extern int x86_cpu_has_vpclmulqdq;
-extern int x86_cpu_has_tzcnt;
 extern int x86_cpu_has_os_save_ymm;
 extern int x86_cpu_has_os_save_zmm;