]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
arm64: zynqmp: Generate u-boot.itb and QSPI image via binman
authorMichal Simek <michal.simek@amd.com>
Fri, 1 Nov 2024 09:17:58 +0000 (10:17 +0100)
committerMichal Simek <michal.simek@amd.com>
Wed, 27 Nov 2024 07:59:03 +0000 (08:59 +0100)
u-boot.itb has been generated via mkimage_fit_atf.sh but it is on the way
out that's why convert it's description to binman.
Compare to script binman description is not able to configure BL31 and BL32
load/entry addresses which should be done separately.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/90b613796aee38158252c8bb1dfc3da0420f089d.1730452668.git.michal.simek@amd.com
arch/arm/dts/Makefile
arch/arm/dts/zynqmp-binman.dts [new file with mode: 0644]
configs/xilinx_zynqmp_virt_defconfig

index 95b552b303bf61dd7343f59c046b3c8560505cf0..cfa358613c458cf7d4789f92e55d4ad4111fdb92 100644 (file)
@@ -320,6 +320,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-02-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-03-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-04-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-05-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-binman.dtb
 
 zynqmp-sc-vek280-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vek280-revA.dtbo
 zynqmp-sc-vek280-revB-dtbs := zynqmp-sc-revC.dtb zynqmp-sc-vek280-revB.dtbo
diff --git a/arch/arm/dts/zynqmp-binman.dts b/arch/arm/dts/zynqmp-binman.dts
new file mode 100644 (file)
index 0000000..df0fdf4
--- /dev/null
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP platforms
+ *
+ * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <config.h>
+
+/dts-v1/;
+/ {
+       binman: binman {
+               multiple-images;
+
+               /* u-boot.itb generation in a static way */
+               itb {
+                       filename = "u-boot.itb";
+                       pad-byte = <0>;
+
+                       fit {
+                               description = "Configuration for Xilinx ZynqMP SoC";
+                               fit,align = <0x8>;
+                               fit,external-offset = <0x0>;
+                               fit,fdt-list = "of-list";
+                               images {
+                                       uboot {
+                                               description = "U-Boot (64-bit)";
+                                               type = "firmware";
+                                               os = "u-boot";
+                                               arch = "arm64";
+                                               compression = "none";
+                                               load = /bits/ 64 <CONFIG_TEXT_BASE>;
+                                               entry = /bits/ 64 <CONFIG_TEXT_BASE>;
+                                               hash {
+                                                       algo = "md5";
+                                               };
+                                               u-boot-nodtb {
+                                               };
+                                       };
+                                       atf {
+                                               description = "Trusted Firmware-A";
+                                               type = "firmware";
+                                               os = "arm-trusted-firmware";
+                                               arch = "arm64";
+                                               compression = "none";
+                                               load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+                                               entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+                                               hash {
+                                                       algo = "md5";
+                                               };
+                                               atf-bl31 {
+                                                       optional;
+                                               };
+                                       };
+                                       tee {
+                                               description = "OP-TEE";
+                                               type = "tee";
+                                               arch = "arm64";
+                                               compression = "none";
+                                               os = "tee";
+                                               load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+                                               entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+                                               tee-os {
+                                                       optional;
+                                               };
+                                       };
+                                       @fdt-SEQ {
+                                               description = "NAME";
+                                               type = "flat_dt";
+                                               arch = "arm64";
+                                               compression = "none";
+                                               load = <0x0 0x100000>;
+                                               hash-1 {
+                                                       algo = "md5";
+                                               };
+                                       };
+                               };
+                               configurations {
+                                       default = "@conf-DEFAULT-SEQ";
+                                       @conf-SEQ {
+                                               description = "NAME";
+                                               firmware = "atf";
+                                               loadables = "tee", "uboot";
+                                               fdt = "fdt-SEQ";
+                                       };
+                               };
+                       };
+               };
+
+#ifdef CONFIG_SYS_SPI_U_BOOT_OFFS
+               /* QSPI image for testing QSPI boot mode */
+               image {
+                       filename = "qspi.bin";
+                       pad-byte = <0>;
+
+                       blob-ext@1 {
+                               offset = <0x0>;
+                               filename = "spl/boot.bin";
+                       };
+                       blob-ext@2 {
+                               offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+                               filename = "u-boot.itb";
+                       };
+                       fdtmap {
+                       };
+               };
+#endif
+       };
+};
index 310efdf2338a1a0ac629f7db32eefba12e265e92..09f487acf0dc64eaf2a838058033c52f02c49de8 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_SYS_PBSIZE=2073
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_BINMAN_SYMBOLS is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
@@ -241,6 +242,8 @@ CONFIG_BMP_32BPP=y
 CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO_NET=y
 CONFIG_VIRTIO_BLK=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman.dtb"
 CONFIG_PANIC_HANG=y
 CONFIG_TPM=y
 CONFIG_SPL_GZIP=y