]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
scsi: mpi3mr: Update MPI headers to revision 37
authorChandrakanth Patil <chandrakanth.patil@broadcom.com>
Wed, 20 Aug 2025 08:41:36 +0000 (14:11 +0530)
committerMartin K. Petersen <martin.petersen@oracle.com>
Tue, 26 Aug 2025 01:39:37 +0000 (21:39 -0400)
Sync MPI header files to revision 37 to match current firmware/spec
definitions.

No functional change.

Signed-off-by: Chandrakanth Patil <chandrakanth.patil@broadcom.com>
Link: https://lore.kernel.org/r/20250820084138.228471-5-chandrakanth.patil@broadcom.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
drivers/scsi/mpi3mr/mpi/mpi30_pci.h
drivers/scsi/mpi3mr/mpi/mpi30_sas.h
drivers/scsi/mpi3mr/mpi/mpi30_transport.h

index 96401eb7e2319eb360bf54362cc14ee64534d9fc..8c8bfbbdd34e6fa7527a217c03da24a416fa8969 100644 (file)
@@ -322,6 +322,9 @@ struct mpi3_man6_gpio_entry {
 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK                       (0x01)
 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE                       (0x00)
 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL                      (0x01)
+#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_WARNING                         (0x00)
+#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_CRITICAL                        (0x01)
+#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_FATAL                           (0x02)
 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP                    (0x00)
 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP            (0x01)
 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT             (0x00)
@@ -1250,6 +1253,37 @@ struct mpi3_io_unit_page17 {
        __le32                             current_key[];
 };
 #define MPI3_IOUNIT17_PAGEVERSION              (0x00)
+struct mpi3_io_unit_page18 {
+       struct mpi3_config_page_header          header;
+       u8                                      flags;
+       u8                                      poll_interval;
+       __le16                                  reserved0a;
+       __le32                                  reserved0c;
+};
+
+#define MPI3_IOUNIT18_PAGEVERSION                                   (0x00)
+#define MPI3_IOUNIT18_FLAGS_DIRECTATTACHED_ENABLE                   (0x01)
+#define MPI3_IOUNIT18_POLLINTERVAL_DISABLE                          (0x00)
+#ifndef MPI3_IOUNIT19_DEVICE_MAX
+#define MPI3_IOUNIT19_DEVICE_MAX                                    (1)
+#endif
+struct mpi3_iounit19_device {
+       __le16                             temperature;
+       __le16                             dev_handle;
+       __le16                             persistent_id;
+       __le16                             reserved06;
+};
+
+#define MPI3_IOUNIT19_DEVICE_TEMPERATURE_UNAVAILABLE                (0x8000)
+struct mpi3_io_unit_page19 {
+       struct mpi3_config_page_header          header;
+       __le16                                  num_devices;
+       __le16                                  reserved0a;
+       __le32                                  reserved0c;
+       struct mpi3_iounit19_device             device[MPI3_IOUNIT19_DEVICE_MAX];
+};
+
+#define MPI3_IOUNIT19_PAGEVERSION                                   (0x00)
 struct mpi3_ioc_page0 {
        struct mpi3_config_page_header         header;
        __le32                             reserved08;
@@ -2356,7 +2390,9 @@ struct mpi3_device0_vd_format {
        __le16     io_throttle_group;
        __le16     io_throttle_group_low;
        __le16     io_throttle_group_high;
-       __le32     reserved0c;
+       u8         vd_abort_to;
+       u8         vd_reset_to;
+       __le16     reserved0e;
 };
 #define MPI3_DEVICE0_VD_STATE_OFFLINE                       (0x00)
 #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED            (0x01)
index 7c15e5851ce428efcbf18cb17191d40aa008c7b8..4eeb11c3c73ef19fbeafdeb80c9cd57428b1892b 100644 (file)
@@ -9,9 +9,11 @@
 #define MPI3_NVME_ENCAP_CMD_MAX               (1)
 #endif
 #define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_MASK      (0x0002)
+#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_SHIFT     (1)
 #define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_FAIL_ONLY (0x0000)
 #define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_ALL       (0x0002)
 #define MPI3_NVME_FLAGS_SUBMISSIONQ_MASK                (0x0001)
+#define MPI3_NVME_FLAGS_SUBMISSIONQ_SHIFT               (0)
 #define MPI3_NVME_FLAGS_SUBMISSIONQ_IO                  (0x0000)
 #define MPI3_NVME_FLAGS_SUBMISSIONQ_ADMIN               (0x0001)
 
index 4a93c67d335ff840b5dfda9710c36999cf2a3d04..190b06508b00bc4485da7cccbc53592f351aff9a 100644 (file)
@@ -11,6 +11,7 @@
 #define MPI3_SAS_DEVICE_INFO_STP_INITIATOR          (0x00000010)
 #define MPI3_SAS_DEVICE_INFO_SMP_INITIATOR          (0x00000008)
 #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_MASK       (0x00000007)
+#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_SHIFT      (0)
 #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_NO_DEVICE  (0x00000000)
 #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_END_DEVICE (0x00000001)
 #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_EXPANDER   (0x00000002)
index 5c522e2531c3d60975deed5461ea944f1a2430d2..28ab2efb3baa45b43307bdbc0337bde73f9f2c72 100644 (file)
@@ -18,7 +18,7 @@ union mpi3_version_union {
 
 #define MPI3_VERSION_MAJOR                                              (3)
 #define MPI3_VERSION_MINOR                                              (0)
-#define MPI3_VERSION_UNIT                                               (35)
+#define MPI3_VERSION_UNIT                                               (37)
 #define MPI3_VERSION_DEV                                                (0)
 #define MPI3_DEVHANDLE_INVALID                                          (0xffff)
 struct mpi3_sysif_oper_queue_indexes {