drm/amd/display: Group scl_data together in resource_build_scaling_params

Move the scl_data.format to be close to other similar parts.

Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 2633e481234f323d04a74a0c231be1cf26ae8c3a..876b0e5eda95f5839d9f4ca10ceb1a06c16becb6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1500,9 +1500,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
                return false;
        }
 
-       pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
-                       pipe_ctx->plane_state->format);
-
        /* Timing borders are part of vactive that we are also supposed to skip in addition
         * to any stream dst offset. Since dm logic assumes dst is in addressable
         * space we need to add the left and top borders to dst offsets temporarily.
@@ -1514,6 +1511,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
        /* Calculate H and V active size */
        pipe_ctx->plane_res.scl_data.h_active = odm_slice_rec.width;
        pipe_ctx->plane_res.scl_data.v_active = odm_slice_rec.height;
+       pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
+                       pipe_ctx->plane_state->format);
 
        /* depends on h_active */
        calculate_recout(pipe_ctx);