;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
(define_insn_reservation "r24k_int_load" 2
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "load"))
"r24k_iss+r24k_ixu_arith")
;; (movn/movz is not matched, we'll need to split condmov to
;; differentiate between integer/float moves)
(define_insn_reservation "r24k_int_arith" 1
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "arith,const,nop,shift,slt"))
"r24k_iss+r24k_ixu_arith")
;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx
;; 3a. jr/jalr consumer
(define_insn_reservation "r24k_int_jump" 1
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "call,jump"))
"r24k_iss+r24k_ixu_arith")
;; 3b. branch consumer
(define_insn_reservation "r24k_int_branch" 1
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "branch"))
"r24k_iss+r24k_ixu_arith")
;; 4. MDU: fully pipelined multiplier
;; mult - delivers result to hi/lo in 1 cycle (pipelined)
(define_insn_reservation "r24k_int_mult" 1
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "imul"))
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined)
(define_insn_reservation "r24k_int_madd" 1
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "imadd"))
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
;; mul - delivers result to gpr in 5 cycles
(define_insn_reservation "r24k_int_mul3" 5
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "imul3"))
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
(define_insn_reservation "r24k_int_mfhilo" 5
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "mfhilo"))
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
(define_insn_reservation "r24k_int_mthilo" 1
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "mthilo"))
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and
;; 8bit, but is tricky to identify.
(define_insn_reservation "r24k_int_div" 36
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "idiv"))
"r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36")
;; 6. Store
(define_insn_reservation "r24k_int_store" 1
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(and (eq_attr "type" "store")
(eq_attr "mode" "!unknown")))
"r24k_iss+r24k_ixu_arith")
;; against store_data_bypass_p, which would then fail because cprestore
;; does not have a normal SET pattern.
(define_insn_reservation "r24k_unknown_store" 1
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(and (eq_attr "type" "store")
(eq_attr "mode" "unknown")))
"r24k_iss+r24k_ixu_arith")
;; 7. Multiple instructions
(define_insn_reservation "r24k_int_multi" 1
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "multi"))
"r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)")
;; rtls. They do not really affect scheduling latency, (blockage affects
;; scheduling via log links, but not used here).
(define_insn_reservation "r24k_int_unknown" 0
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "unknown"))
"r24k_iss")
;; 9. Prefetch
(define_insn_reservation "r24k_int_prefetch" 1
- (and (eq_attr "cpu" "24k,24kx")
+ (and (eq_attr "cpu" "24kc,24kf,24kx")
(eq_attr "type" "prefetch,prefetchx"))
"r24k_iss+r24k_ixu_arith")
;; fadd, fabs, fneg
(define_insn_reservation "r24k_fadd" 8
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(eq_attr "type" "fadd,fabs,fneg"))
"r24k_fpu_iss")
;; fmove, fcmove
(define_insn_reservation "r24k_fmove" 8
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(eq_attr "type" "fmove,condmove"))
"r24k_fpu_iss")
;; fload
(define_insn_reservation "r24k_fload" 6
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(eq_attr "type" "fpload,fpidxload"))
"r24k_fpu_iss")
;; fstore
(define_insn_reservation "r24k_fstore" 2
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(eq_attr "type" "fpstore"))
"r24k_fpu_iss")
;; fmul, fmadd
(define_insn_reservation "r24k_fmul_sf" 8
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
"r24k_fpu_iss")
(define_insn_reservation "r24k_fmul_df" 10
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
"r24k_fpu_iss,(r24k_fpu_arith*2)")
;; fdiv, fsqrt, frsqrt
(define_insn_reservation "r24k_fdiv_sf" 34
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(and (eq_attr "type" "fdiv,fsqrt,frsqrt")
(eq_attr "mode" "SF")))
"r24k_fpu_iss,(r24k_fpu_arith*26)")
(define_insn_reservation "r24k_fdiv_df" 64
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "DF")))
"r24k_fpu_iss,(r24k_fpu_arith*56)")
;; frsqrt
(define_insn_reservation "r24k_frsqrt_df" 70
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
"r24k_fpu_iss,(r24k_fpu_arith*60)")
;; fcmp
(define_insn_reservation "r24k_fcmp" 4
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(eq_attr "type" "fcmp"))
"r24k_fpu_iss")
;; fcvt (cvt.d.s, cvt.[sd].[wl])
(define_insn_reservation "r24k_fcvt_i2f_s2d" 8
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "I2S,I2D,S2D")))
"r24k_fpu_iss")
;; fcvt (cvt.s.d)
(define_insn_reservation "r24k_fcvt_s2d" 12
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "D2S")))
"r24k_fpu_iss")
;; fcvt (cvt.[wl].[sd], etc)
(define_insn_reservation "r24k_fcvt_f2i" 10
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "S2I,D2I")))
"r24k_fpu_iss")
;; fxfer (mfc1, mfhc1, mtc1, mthc1)
(define_insn_reservation "r24k_fxfer" 4
- (and (eq_attr "cpu" "24k")
+ (and (eq_attr "cpu" "24kf")
(eq_attr "type" "xfer"))
"r24k_fpu_iss")
/* MIPS32 Release 2 */
{ "m4k", PROCESSOR_M4K, 33 },
- { "24k", PROCESSOR_24K, 33 },
- { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
- { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
- { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
+ { "4kec", PROCESSOR_4KC, 33 },
+ { "4kem", PROCESSOR_4KC, 33 },
+ { "4kep", PROCESSOR_4KP, 33 },
+ { "24kc", PROCESSOR_24KC, 33 }, /* 24K no FPU */
+ { "24kf", PROCESSOR_24KF, 33 }, /* 24K 1:2 FPU */
+ { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
+ { "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
+ { "24kef", PROCESSOR_24KF, 33 },
+ { "24kex", PROCESSOR_24KX, 33 },
+ { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
+ { "34kf", PROCESSOR_24KF, 33 },
+ { "34kx", PROCESSOR_24KX, 33 },
/* MIPS64 */
{ "5kc", PROCESSOR_5KC, 64 },
{ /* 20KC */
DEFAULT_COSTS
},
- { /* 24k */
+ { /* 24KC */
+ SOFT_FP_COSTS,
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (5), /* int_mult_di */
+ COSTS_N_INSNS (41), /* int_div_si */
+ COSTS_N_INSNS (41), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 24KF */
COSTS_N_INSNS (8), /* fp_add */
COSTS_N_INSNS (8), /* fp_mult_sf */
COSTS_N_INSNS (10), /* fp_mult_df */
1, /* branch_cost */
4 /* memory_latency */
},
- { /* 24kx */
+ { /* 24KX */
COSTS_N_INSNS (4), /* fp_add */
COSTS_N_INSNS (4), /* fp_mult_sf */
COSTS_N_INSNS (5), /* fp_mult_df */