5.15-stable patches

added patches:
	drm-amdgpu-gfx10-add-wraparound-gpu-counter-check-for-apus-as-well.patch
	drm-amdgpu-gfx9-switch-to-golden-tsc-registers-for-renoir.patch

diff --git a/queue-5.15/drm-amdgpu-gfx10-add-wraparound-gpu-counter-check-for-apus-as-well.patch b/queue-5.15/drm-amdgpu-gfx10-add-wraparound-gpu-counter-check-for-apus-as-well.patch
new file mode 100644 (file)
index 0000000..111ad25
--- /dev/null
+++ b/queue-5.15/drm-amdgpu-gfx10-add-wraparound-gpu-counter-check-for-apus-as-well.patch
@@ -0,0 +1,42 @@
+From 244ee398855df2adc7d3ac5702b58424a5f684cc Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 18 Nov 2021 14:33:23 -0500
+Subject: drm/amdgpu/gfx10: add wraparound gpu counter check for APUs as well
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 244ee398855df2adc7d3ac5702b58424a5f684cc upstream.
+
+Apply the same check we do for dGPUs for APUs as well.
+
+Acked-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |   15 +++++++++++++--
+ 1 file changed, 13 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -7729,8 +7729,19 @@ static uint64_t gfx_v10_0_get_gpu_clock_
+       switch (adev->asic_type) {
+       case CHIP_VANGOGH:
+       case CHIP_YELLOW_CARP:
+-              clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
+-                      ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
++              preempt_disable();
++              clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
++              clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
++              hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
++              /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
++               * roughly every 42 seconds.
++               */
++              if (hi_check != clock_hi) {
++                      clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
++                      clock_hi = hi_check;
++              }
++              preempt_enable();
++              clock = clock_lo | (clock_hi << 32ULL);
+               break;
+       default:
+               preempt_disable();

diff --git a/queue-5.15/drm-amdgpu-gfx9-switch-to-golden-tsc-registers-for-renoir.patch b/queue-5.15/drm-amdgpu-gfx9-switch-to-golden-tsc-registers-for-renoir.patch
new file mode 100644 (file)
index 0000000..45f406b
--- /dev/null
+++ b/queue-5.15/drm-amdgpu-gfx9-switch-to-golden-tsc-registers-for-renoir.patch
@@ -0,0 +1,85 @@
+From 53af98c091bc42fd9ec64cfabc40da4e5f3aae93 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 18 Nov 2021 14:50:37 -0500
+Subject: drm/amdgpu/gfx9: switch to golden tsc registers for renoir+
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 53af98c091bc42fd9ec64cfabc40da4e5f3aae93 upstream.
+
+Renoir and newer gfx9 APUs have new TSC register that is
+not part of the gfxoff tile, so it can be read without
+needing to disable gfx off.
+
+Acked-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |   46 +++++++++++++++++++++++++---------
+ 1 file changed, 35 insertions(+), 11 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -140,6 +140,11 @@ MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bi
+ #define mmTCP_CHAN_STEER_5_ARCT                                                               0x0b0c
+ #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX                                                      0
+ 
++#define mmGOLDEN_TSC_COUNT_UPPER_Renoir                0x0025
++#define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX       1
++#define mmGOLDEN_TSC_COUNT_LOWER_Renoir                0x0026
++#define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX       1
++
+ enum ta_ras_gfx_subblock {
+       /*CPC*/
+       TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
+@@ -4228,19 +4233,38 @@ failed_kiq_read:
+ 
+ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
+ {
+-      uint64_t clock;
++      uint64_t clock, clock_lo, clock_hi, hi_check;
+ 
+-      amdgpu_gfx_off_ctrl(adev, false);
+-      mutex_lock(&adev->gfx.gpu_clock_mutex);
+-      if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
+-              clock = gfx_v9_0_kiq_read_clock(adev);
+-      } else {
+-              WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
+-              clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
+-                      ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
++      switch (adev->asic_type) {
++      case CHIP_RENOIR:
++              preempt_disable();
++              clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir);
++              clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir);
++              hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir);
++              /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
++               * roughly every 42 seconds.
++               */
++              if (hi_check != clock_hi) {
++                      clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir);
++                      clock_hi = hi_check;
++              }
++              preempt_enable();
++              clock = clock_lo | (clock_hi << 32ULL);
++              break;
++      default:
++              amdgpu_gfx_off_ctrl(adev, false);
++              mutex_lock(&adev->gfx.gpu_clock_mutex);
++              if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
++                      clock = gfx_v9_0_kiq_read_clock(adev);
++              } else {
++                      WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
++                      clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
++                              ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
++              }
++              mutex_unlock(&adev->gfx.gpu_clock_mutex);
++              amdgpu_gfx_off_ctrl(adev, true);
++              break;
+       }
+-      mutex_unlock(&adev->gfx.gpu_clock_mutex);
+-      amdgpu_gfx_off_ctrl(adev, true);
+       return clock;
+ }
+ 

diff --git a/queue-5.15/series b/queue-5.15/series
index 572684676b52fbc3bf693c7ede8351521920c7d6..e4a80a8b8f86af94ad5d7a4518aac429aee4bcb0 100644 (file)
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -175,3 +175,5 @@ firmware-arm_scmi-fix-type-error-in-sensor-protocol.patch
 docs-accounting-update-delay-accounting.rst-reference.patch
 blk-mq-cancel-blk-mq-dispatch-work-in-both-blk_cleanup_queue-and-disk_release.patch
 block-avoid-to-quiesce-queue-in-elevator_init_mq.patch
+drm-amdgpu-gfx10-add-wraparound-gpu-counter-check-for-apus-as-well.patch
+drm-amdgpu-gfx9-switch-to-golden-tsc-registers-for-renoir.patch