re PR target/34930 (ICE in instantiate_virtual_regs_in_insn with vector splat load)

        PR target/34930
        * function.c (instantiate_virtual_regs_in_insn): Reload address
        before falling back to reloading the whole operand.

From-SVN: r132317

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 23d2bec85a74024761cf79fd0118b25f4502c051..936ae64ffbf85f9d41e17d84c8d7a46568fa1743 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2008-02-14  Michael Matz  <matz@suse.de>
+
+       PR target/34930
+       * function.c (instantiate_virtual_regs_in_insn): Reload address
+       before falling back to reloading the whole operand.
+
 2008-02-14  Andreas Krebbel  <krebbel1@de.ibm.com>
 
        * config/s390/s390.c (s390_mainpool_start): Emit the pool

diff --git a/gcc/function.c b/gcc/function.c
index 514d1a6e9b0b0648303fe019f095330abb5149c7..d3fbd17c8cceee79e8a7a1801bbd91a5b5247738 100644 (file)
--- a/gcc/function.c
+++ b/gcc/function.c
@@ -1468,6 +1468,20 @@ instantiate_virtual_regs_in_insn (rtx insn)
 
            start_sequence ();
            x = replace_equiv_address (x, addr);
+           /* It may happen that the address with the virtual reg
+              was valid (e.g. based on the virtual stack reg, which might
+              be acceptable to the predicates with all offsets), whereas
+              the address now isn't anymore, for instance when the address
+              is still offsetted, but the base reg isn't virtual-stack-reg
+              anymore.  Below we would do a force_reg on the whole operand,
+              but this insn might actually only accept memory.  Hence,
+              before doing that last resort, try to reload the address into
+              a register, so this operand stays a MEM.  */
+           if (!safe_insn_predicate (insn_code, i, x))
+             {
+               addr = force_reg (GET_MODE (addr), addr);
+               x = replace_equiv_address (x, addr);
+             }
            seq = get_insns ();
            end_sequence ();
            if (seq)