--- /dev/null
+From 18932a28419596bc9403770f5d8a108c5433fe59 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 25 Apr 2013 13:55:15 -0400
+Subject: drm/radeon: add some new SI PCI ids
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 18932a28419596bc9403770f5d8a108c5433fe59 upstream.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ include/drm/drm_pciids.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/include/drm/drm_pciids.h
++++ b/include/drm/drm_pciids.h
+@@ -227,6 +227,7 @@
+ {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+@@ -234,11 +235,13 @@
+ {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
--- /dev/null
+From 7c1c7c18fc752b2a1d07597286467ef186312463 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 5 Apr 2013 10:28:08 -0400
+Subject: drm/radeon/dce6: add missing display reg for tiling setup
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 7c1c7c18fc752b2a1d07597286467ef186312463 upstream.
+
+A new tiling config register for the display blocks was
+added on DCE6.
+
+May fix:
+https://bugs.freedesktop.org/show_bug.cgi?id=62889
+https://bugs.freedesktop.org/show_bug.cgi?id=57919
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/ni.c | 2 ++
+ drivers/gpu/drm/radeon/nid.h | 4 ++++
+ drivers/gpu/drm/radeon/si.c | 1 +
+ drivers/gpu/drm/radeon/sid.h | 2 ++
+ 4 files changed, 9 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/ni.c
++++ b/drivers/gpu/drm/radeon/ni.c
+@@ -619,6 +619,8 @@ static void cayman_gpu_init(struct radeo
+
+ WREG32(GB_ADDR_CONFIG, gb_addr_config);
+ WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
++ if (ASIC_IS_DCE6(rdev))
++ WREG32(DMIF_ADDR_CALC, gb_addr_config);
+ WREG32(HDP_ADDR_CONFIG, gb_addr_config);
+ WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
+ WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
+--- a/drivers/gpu/drm/radeon/nid.h
++++ b/drivers/gpu/drm/radeon/nid.h
+@@ -45,6 +45,10 @@
+ #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
+
+ #define DMIF_ADDR_CONFIG 0xBD4
++
++/* DCE6 only */
++#define DMIF_ADDR_CALC 0xC00
++
+ #define SRBM_GFX_CNTL 0x0E44
+ #define RINGID(x) (((x) & 0x3) << 0)
+ #define VMID(x) (((x) & 0x7) << 0)
+--- a/drivers/gpu/drm/radeon/si.c
++++ b/drivers/gpu/drm/radeon/si.c
+@@ -1659,6 +1659,7 @@ static void si_gpu_init(struct radeon_de
+
+ WREG32(GB_ADDR_CONFIG, gb_addr_config);
+ WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
++ WREG32(DMIF_ADDR_CALC, gb_addr_config);
+ WREG32(HDP_ADDR_CONFIG, gb_addr_config);
+ WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
+ WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
+--- a/drivers/gpu/drm/radeon/sid.h
++++ b/drivers/gpu/drm/radeon/sid.h
+@@ -60,6 +60,8 @@
+
+ #define DMIF_ADDR_CONFIG 0xBD4
+
++#define DMIF_ADDR_CALC 0xC00
++
+ #define SRBM_STATUS 0xE50
+
+ #define SRBM_SOFT_RESET 0x0E60
--- /dev/null
+From abf1457bbbe4c62066bd03c6d31837dea28644dc Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 10 Apr 2013 19:08:14 -0400
+Subject: drm/radeon: disable the crtcs in mc_stop (evergreen+) (v2)
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit abf1457bbbe4c62066bd03c6d31837dea28644dc upstream.
+
+Just disabling the mem requests should be enough, but
+that doesn't seem to work correctly on efi systems.
+
+May fix:
+https://bugs.freedesktop.org/show_bug.cgi?id=57567
+https://bugs.freedesktop.org/show_bug.cgi?id=43655
+https://bugzilla.kernel.org/show_bug.cgi?id=56441
+
+v2: blank displays first, then disable.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -1353,6 +1353,7 @@ void evergreen_mc_stop(struct radeon_dev
+ tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
+ if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
+ radeon_wait_for_vblank(rdev, i);
++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
+ WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
+ }
+@@ -1360,8 +1361,10 @@ void evergreen_mc_stop(struct radeon_dev
+ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
+ if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
+ radeon_wait_for_vblank(rdev, i);
++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
+ WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ }
+ }
+ /* wait for the next frame */
+@@ -1371,6 +1374,15 @@ void evergreen_mc_stop(struct radeon_dev
+ break;
+ udelay(1);
+ }
++
++ /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
++ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
++ tmp &= ~EVERGREEN_CRTC_MASTER_EN;
++ WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
++ save->crtc_enabled[i] = false;
++ /* ***** */
+ } else {
+ save->crtc_enabled[i] = false;
+ }
--- /dev/null
+From bf05d9985111f85ed6922c134567b96eb789283b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 18 Mar 2013 17:12:50 -0400
+Subject: drm/radeon: don't use get_engine_clock() on APUs
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit bf05d9985111f85ed6922c134567b96eb789283b upstream.
+
+It doesn't work reliably. Just report back the currently
+selected engine clock.
+
+Partially fixes:
+https://bugs.freedesktop.org/show_bug.cgi?id=62493
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_pm.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_pm.c
++++ b/drivers/gpu/drm/radeon/radeon_pm.c
+@@ -843,7 +843,11 @@ static int radeon_debugfs_pm_info(struct
+ struct radeon_device *rdev = dev->dev_private;
+
+ seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
+- seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
++ /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
++ if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
++ seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
++ else
++ seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
+ seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
+ if (rdev->asic->pm.get_memory_clock)
+ seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
--- /dev/null
+From 367cbe2fec9b57b72605e2ac4cfd4f2fa823a256 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 4 Apr 2013 14:59:35 -0400
+Subject: drm/radeon: fix typo in rv515_mc_resume()
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 367cbe2fec9b57b72605e2ac4cfd4f2fa823a256 upstream.
+
+Doesn't affect anything as the same address gets written
+in both cases.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/rv515.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/rv515.c
++++ b/drivers/gpu/drm/radeon/rv515.c
+@@ -348,7 +348,7 @@ void rv515_mc_resume(struct radeon_devic
+ /* update crtc base addresses */
+ for (i = 0; i < rdev->num_crtc; i++) {
+ if (rdev->family >= CHIP_RV770) {
+- if (i == 1) {
++ if (i == 0) {
+ WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
+ upper_32_bits(rdev->mc.vram_start));
+ WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
--- /dev/null
+From 968c01664ccbe0e46c19a1af662c4c266a904203 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 10 Apr 2013 09:58:42 -0400
+Subject: drm/radeon: properly lock disp in mc_stop/resume for evergreen+
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 968c01664ccbe0e46c19a1af662c4c266a904203 upstream.
+
+Need to wait for the new addresses to take affect before
+re-enabling the MC.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c | 47 ++++++++++++++++++++++++++++++---
+ drivers/gpu/drm/radeon/evergreen_reg.h | 2 +
+ 2 files changed, 45 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -1354,18 +1354,14 @@ void evergreen_mc_stop(struct radeon_dev
+ if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
+ radeon_wait_for_vblank(rdev, i);
+ tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
+- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
+- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ }
+ } else {
+ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
+ if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
+ radeon_wait_for_vblank(rdev, i);
+ tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
+- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
+- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ }
+ }
+ /* wait for the next frame */
+@@ -1392,6 +1388,22 @@ void evergreen_mc_stop(struct radeon_dev
+ }
+ /* wait for the MC to settle */
+ udelay(100);
++
++ /* lock double buffered regs */
++ for (i = 0; i < rdev->num_crtc; i++) {
++ if (save->crtc_enabled[i]) {
++ tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
++ if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
++ tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
++ WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
++ }
++ tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
++ if (!(tmp & 1)) {
++ tmp |= 1;
++ WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++ }
++ }
++ }
+ }
+
+ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
+@@ -1413,6 +1425,33 @@ void evergreen_mc_resume(struct radeon_d
+ WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
+ WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
+
++ /* unlock regs and wait for update */
++ for (i = 0; i < rdev->num_crtc; i++) {
++ if (save->crtc_enabled[i]) {
++ tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
++ if ((tmp & 0x3) != 0) {
++ tmp &= ~0x3;
++ WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
++ }
++ tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
++ if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
++ tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
++ WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
++ }
++ tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
++ if (tmp & 1) {
++ tmp &= ~1;
++ WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++ }
++ for (j = 0; j < rdev->usec_timeout; j++) {
++ tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
++ if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
++ break;
++ udelay(1);
++ }
++ }
++ }
++
+ /* unblackout the MC */
+ tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
+ tmp &= ~BLACKOUT_MODE_MASK;
+--- a/drivers/gpu/drm/radeon/evergreen_reg.h
++++ b/drivers/gpu/drm/radeon/evergreen_reg.h
+@@ -225,6 +225,8 @@
+ #define EVERGREEN_CRTC_STATUS_POSITION 0x6e90
+ #define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
+ #define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4
++#define EVERGREEN_MASTER_UPDATE_LOCK 0x6ef4
++#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
+
+ #define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0
+ #define EVERGREEN_DC_GPIO_HPD_A 0x64b4
--- /dev/null
+From 2f86e2ede39a98650c2d465857405ef1c51372b1 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 10 Apr 2013 09:47:05 -0400
+Subject: drm/radeon: properly lock disp in mc_stop/resume for r5xx-r7xx
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 2f86e2ede39a98650c2d465857405ef1c51372b1 upstream.
+
+Need to wait for the new addresses to take affect before
+re-enabling the MC.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/r500_reg.h | 1
+ drivers/gpu/drm/radeon/rv515.c | 43 ++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 44 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/r500_reg.h
++++ b/drivers/gpu/drm/radeon/r500_reg.h
+@@ -357,6 +357,7 @@
+ #define AVIVO_D1CRTC_FRAME_COUNT 0x60a4
+ #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
+
++#define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0
+ #define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
+
+ /* master controls */
+--- a/drivers/gpu/drm/radeon/rv515.c
++++ b/drivers/gpu/drm/radeon/rv515.c
+@@ -338,6 +338,22 @@ void rv515_mc_stop(struct radeon_device
+ }
+ /* wait for the MC to settle */
+ udelay(100);
++
++ /* lock double buffered regs */
++ for (i = 0; i < rdev->num_crtc; i++) {
++ if (save->crtc_enabled[i]) {
++ tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
++ if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
++ tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
++ WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
++ }
++ tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
++ if (!(tmp & 1)) {
++ tmp |= 1;
++ WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++ }
++ }
++ }
+ }
+
+ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
+@@ -367,6 +383,33 @@ void rv515_mc_resume(struct radeon_devic
+ }
+ WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
+
++ /* unlock regs and wait for update */
++ for (i = 0; i < rdev->num_crtc; i++) {
++ if (save->crtc_enabled[i]) {
++ tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
++ if ((tmp & 0x3) != 0) {
++ tmp &= ~0x3;
++ WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
++ }
++ tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
++ if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
++ tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
++ WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
++ }
++ tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
++ if (tmp & 1) {
++ tmp &= ~1;
++ WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++ }
++ for (j = 0; j < rdev->usec_timeout; j++) {
++ tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
++ if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
++ break;
++ udelay(1);
++ }
++ }
++ }
++
+ if (rdev->family >= CHIP_R600) {
+ /* unblackout the MC */
+ if (rdev->family >= CHIP_RV770)
--- /dev/null
+From 10257a6d8359c41407eb26b7ad7bf710a7e00155 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 9 Apr 2013 18:49:59 -0400
+Subject: drm/radeon: update wait_for_vblank for evergreen+
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 10257a6d8359c41407eb26b7ad7bf710a7e00155 upstream.
+
+Properly wait for the next vblank region. The previous
+code didn't always wait long enough depending on the timing.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c | 44 ++++++++++++++++++++++++++++++-------
+ 1 file changed, 36 insertions(+), 8 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -105,6 +105,27 @@ void evergreen_fix_pci_max_read_req_size
+ }
+ }
+
++static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
++{
++ if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
++ return true;
++ else
++ return false;
++}
++
++static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
++{
++ u32 pos1, pos2;
++
++ pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
++ pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
++
++ if (pos1 != pos2)
++ return true;
++ else
++ return false;
++}
++
+ /**
+ * dce4_wait_for_vblank - vblank wait asic callback.
+ *
+@@ -115,21 +136,28 @@ void evergreen_fix_pci_max_read_req_size
+ */
+ void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
+ {
+- int i;
++ unsigned i = 0;
+
+ if (crtc >= rdev->num_crtc)
+ return;
+
+- if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
+- for (i = 0; i < rdev->usec_timeout; i++) {
+- if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
++ if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
++ return;
++
++ /* depending on when we hit vblank, we may be close to active; if so,
++ * wait for another frame.
++ */
++ while (dce4_is_in_vblank(rdev, crtc)) {
++ if (i++ % 100 == 0) {
++ if (!dce4_is_counter_moving(rdev, crtc))
+ break;
+- udelay(1);
+ }
+- for (i = 0; i < rdev->usec_timeout; i++) {
+- if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
++ }
++
++ while (!dce4_is_in_vblank(rdev, crtc)) {
++ if (i++ % 100 == 0) {
++ if (!dce4_is_counter_moving(rdev, crtc))
+ break;
+- udelay(1);
+ }
+ }
+ }
--- /dev/null
+From 2b48b968c0d00aa5ab520b65a15a4f374cda7dda Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 9 Apr 2013 18:32:01 -0400
+Subject: drm/radeon: update wait_for_vblank for r1xx-r4xx
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 2b48b968c0d00aa5ab520b65a15a4f374cda7dda upstream.
+
+Properly wait for the next vblank region. The previous
+code didn't always wait long enough depending on the timing.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/r100.c | 77 ++++++++++++++++++++++++++++--------------
+ 1 file changed, 53 insertions(+), 24 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/r100.c
++++ b/drivers/gpu/drm/radeon/r100.c
+@@ -69,6 +69,38 @@ MODULE_FIRMWARE(FIRMWARE_R520);
+ * and others in some cases.
+ */
+
++static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
++{
++ if (crtc == 0) {
++ if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
++ return true;
++ else
++ return false;
++ } else {
++ if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
++ return true;
++ else
++ return false;
++ }
++}
++
++static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
++{
++ u32 vline1, vline2;
++
++ if (crtc == 0) {
++ vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
++ vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
++ } else {
++ vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
++ vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
++ }
++ if (vline1 != vline2)
++ return true;
++ else
++ return false;
++}
++
+ /**
+ * r100_wait_for_vblank - vblank wait asic callback.
+ *
+@@ -79,36 +111,33 @@ MODULE_FIRMWARE(FIRMWARE_R520);
+ */
+ void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
+ {
+- int i;
++ unsigned i = 0;
+
+ if (crtc >= rdev->num_crtc)
+ return;
+
+ if (crtc == 0) {
+- if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
+- for (i = 0; i < rdev->usec_timeout; i++) {
+- if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
+- break;
+- udelay(1);
+- }
+- for (i = 0; i < rdev->usec_timeout; i++) {
+- if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
+- break;
+- udelay(1);
+- }
+- }
++ if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
++ return;
+ } else {
+- if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
+- for (i = 0; i < rdev->usec_timeout; i++) {
+- if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
+- break;
+- udelay(1);
+- }
+- for (i = 0; i < rdev->usec_timeout; i++) {
+- if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
+- break;
+- udelay(1);
+- }
++ if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
++ return;
++ }
++
++ /* depending on when we hit vblank, we may be close to active; if so,
++ * wait for another frame.
++ */
++ while (r100_is_in_vblank(rdev, crtc)) {
++ if (i++ % 100 == 0) {
++ if (!r100_is_counter_moving(rdev, crtc))
++ break;
++ }
++ }
++
++ while (!r100_is_in_vblank(rdev, crtc)) {
++ if (i++ % 100 == 0) {
++ if (!r100_is_counter_moving(rdev, crtc))
++ break;
+ }
+ }
+ }
--- /dev/null
+From bea5497bfc1067620c8c8e9d37a42e0bb6d7d7fa Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 9 Apr 2013 18:41:15 -0400
+Subject: drm/radeon: update wait_for_vblank for r5xx-r7xx
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit bea5497bfc1067620c8c8e9d37a42e0bb6d7d7fa upstream.
+
+Properly wait for the next vblank region. The previous
+code didn't always wait long enough depending on the timing.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/rs600.c | 52 ++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 44 insertions(+), 8 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/rs600.c
++++ b/drivers/gpu/drm/radeon/rs600.c
+@@ -52,23 +52,59 @@ static const u32 crtc_offsets[2] =
+ AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
+ };
+
++static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
++{
++ if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
++ return true;
++ else
++ return false;
++}
++
++static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
++{
++ u32 pos1, pos2;
++
++ pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
++ pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
++
++ if (pos1 != pos2)
++ return true;
++ else
++ return false;
++}
++
++/**
++ * avivo_wait_for_vblank - vblank wait asic callback.
++ *
++ * @rdev: radeon_device pointer
++ * @crtc: crtc to wait for vblank on
++ *
++ * Wait for vblank on the requested crtc (r5xx-r7xx).
++ */
+ void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
+ {
+- int i;
++ unsigned i = 0;
+
+ if (crtc >= rdev->num_crtc)
+ return;
+
+- if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) {
+- for (i = 0; i < rdev->usec_timeout; i++) {
+- if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK))
++ if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
++ return;
++
++ /* depending on when we hit vblank, we may be close to active; if so,
++ * wait for another frame.
++ */
++ while (avivo_is_in_vblank(rdev, crtc)) {
++ if (i++ % 100 == 0) {
++ if (!avivo_is_counter_moving(rdev, crtc))
+ break;
+- udelay(1);
+ }
+- for (i = 0; i < rdev->usec_timeout; i++) {
+- if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
++ }
++
++ while (!avivo_is_in_vblank(rdev, crtc)) {
++ if (i++ % 100 == 0) {
++ if (!avivo_is_counter_moving(rdev, crtc))
+ break;
+- udelay(1);
+ }
+ }
+ }
--- /dev/null
+From 411678288d61ba17afe1f8afed92200be6bbc65d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 1 Apr 2013 16:06:25 -0400
+Subject: drm/radeon: use frac fb div on RS780/RS880
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 411678288d61ba17afe1f8afed92200be6bbc65d upstream.
+
+Monitors seem to prefer it. Fixes:
+https://bugs.freedesktop.org/show_bug.cgi?id=37696
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atombios_crtc.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/atombios_crtc.c
++++ b/drivers/gpu/drm/radeon/atombios_crtc.c
+@@ -557,6 +557,9 @@ static u32 atombios_adjust_pll(struct dr
+ /* use frac fb div on APUs */
+ if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
+ radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
++ /* use frac fb div on RS780/RS880 */
++ if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
++ radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
+ if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
+ radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
+ } else {
drm-i915-ensure-single-initialization-and-cleanup-of-backlight-device.patch
drm-i915-fixup-oops-in-the-pipe-config-computation.patch
drm-i915-fall-back-to-bit-banging-mode-for-dvo-transmitter-detection.patch
+drm-radeon-don-t-use-get_engine_clock-on-apus.patch
+drm-radeon-use-frac-fb-div-on-rs780-rs880.patch
+drm-radeon-fix-typo-in-rv515_mc_resume.patch
+drm-radeon-dce6-add-missing-display-reg-for-tiling-setup.patch
+drm-radeon-update-wait_for_vblank-for-r5xx-r7xx.patch
+drm-radeon-update-wait_for_vblank-for-evergreen.patch
+drm-radeon-properly-lock-disp-in-mc_stop-resume-for-evergreen.patch
+drm-radeon-properly-lock-disp-in-mc_stop-resume-for-r5xx-r7xx.patch
+drm-radeon-update-wait_for_vblank-for-r1xx-r4xx.patch
+drm-radeon-disable-the-crtcs-in-mc_stop-evergreen-v2.patch
+drm-radeon-add-some-new-si-pci-ids.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
