pinctrl: rockchip: Add support for RK3528

Add gpio and pinctrl support for the 5 GPIO banks on RK3528.

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/20250228064024.3200000-4-jonas@kwiboo.se
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 15145882950f714bb9d4f5a5c653084b0d1af4b7..930c454e0cec7d88d66b2967fe8f14c915429e63 100644 (file)
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2003,6 +2003,115 @@ static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
        return 0;
 }
 
+#define RK3528_DRV_BITS_PER_PIN                8
+#define RK3528_DRV_PINS_PER_REG                2
+#define RK3528_DRV_GPIO0_OFFSET                0x100
+#define RK3528_DRV_GPIO1_OFFSET                0x20120
+#define RK3528_DRV_GPIO2_OFFSET                0x30160
+#define RK3528_DRV_GPIO3_OFFSET                0x20190
+#define RK3528_DRV_GPIO4_OFFSET                0x101C0
+
+static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+                                      int pin_num, struct regmap **regmap,
+                                      int *reg, u8 *bit)
+{
+       struct rockchip_pinctrl *info = bank->drvdata;
+
+       *regmap = info->regmap_base;
+
+       if (bank->bank_num == 0)
+               *reg = RK3528_DRV_GPIO0_OFFSET;
+       else if (bank->bank_num == 1)
+               *reg = RK3528_DRV_GPIO1_OFFSET;
+       else if (bank->bank_num == 2)
+               *reg = RK3528_DRV_GPIO2_OFFSET;
+       else if (bank->bank_num == 3)
+               *reg = RK3528_DRV_GPIO3_OFFSET;
+       else if (bank->bank_num == 4)
+               *reg = RK3528_DRV_GPIO4_OFFSET;
+       else
+               dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+
+       *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
+       *bit = pin_num % RK3528_DRV_PINS_PER_REG;
+       *bit *= RK3528_DRV_BITS_PER_PIN;
+
+       return 0;
+}
+
+#define RK3528_PULL_BITS_PER_PIN               2
+#define RK3528_PULL_PINS_PER_REG               8
+#define RK3528_PULL_GPIO0_OFFSET               0x200
+#define RK3528_PULL_GPIO1_OFFSET               0x20210
+#define RK3528_PULL_GPIO2_OFFSET               0x30220
+#define RK3528_PULL_GPIO3_OFFSET               0x20230
+#define RK3528_PULL_GPIO4_OFFSET               0x10240
+
+static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+                                       int pin_num, struct regmap **regmap,
+                                       int *reg, u8 *bit)
+{
+       struct rockchip_pinctrl *info = bank->drvdata;
+
+       *regmap = info->regmap_base;
+
+       if (bank->bank_num == 0)
+               *reg = RK3528_PULL_GPIO0_OFFSET;
+       else if (bank->bank_num == 1)
+               *reg = RK3528_PULL_GPIO1_OFFSET;
+       else if (bank->bank_num == 2)
+               *reg = RK3528_PULL_GPIO2_OFFSET;
+       else if (bank->bank_num == 3)
+               *reg = RK3528_PULL_GPIO3_OFFSET;
+       else if (bank->bank_num == 4)
+               *reg = RK3528_PULL_GPIO4_OFFSET;
+       else
+               dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+
+       *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
+       *bit = pin_num % RK3528_PULL_PINS_PER_REG;
+       *bit *= RK3528_PULL_BITS_PER_PIN;
+
+       return 0;
+}
+
+#define RK3528_SMT_BITS_PER_PIN                1
+#define RK3528_SMT_PINS_PER_REG                8
+#define RK3528_SMT_GPIO0_OFFSET                0x400
+#define RK3528_SMT_GPIO1_OFFSET                0x20410
+#define RK3528_SMT_GPIO2_OFFSET                0x30420
+#define RK3528_SMT_GPIO3_OFFSET                0x20430
+#define RK3528_SMT_GPIO4_OFFSET                0x10440
+
+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+                                          int pin_num,
+                                          struct regmap **regmap,
+                                          int *reg, u8 *bit)
+{
+       struct rockchip_pinctrl *info = bank->drvdata;
+
+       *regmap = info->regmap_base;
+
+       if (bank->bank_num == 0)
+               *reg = RK3528_SMT_GPIO0_OFFSET;
+       else if (bank->bank_num == 1)
+               *reg = RK3528_SMT_GPIO1_OFFSET;
+       else if (bank->bank_num == 2)
+               *reg = RK3528_SMT_GPIO2_OFFSET;
+       else if (bank->bank_num == 3)
+               *reg = RK3528_SMT_GPIO3_OFFSET;
+       else if (bank->bank_num == 4)
+               *reg = RK3528_SMT_GPIO4_OFFSET;
+       else
+               dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+
+       *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
+       *bit = pin_num % RK3528_SMT_PINS_PER_REG;
+       *bit *= RK3528_SMT_BITS_PER_PIN;
+
+       return 0;
+}
+
 #define RK3562_DRV_BITS_PER_PIN                8
 #define RK3562_DRV_PINS_PER_REG                2
 #define RK3562_DRV_GPIO0_OFFSET                0x20070
@@ -2640,7 +2749,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
                rmask_bits = RK3588_DRV_BITS_PER_PIN;
                ret = strength;
                goto config;
-       } else if (ctrl->type == RK3562 ||
+       } else if (ctrl->type == RK3528 ||
+                  ctrl->type == RK3562 ||
                   ctrl->type == RK3568) {
                rmask_bits = RK3568_DRV_BITS_PER_PIN;
                ret = (1 << (strength + 1)) - 1;
@@ -2785,6 +2895,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
        case RK3328:
        case RK3368:
        case RK3399:
+       case RK3528:
        case RK3562:
        case RK3568:
        case RK3576:
@@ -2846,6 +2957,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
        case RK3328:
        case RK3368:
        case RK3399:
+       case RK3528:
        case RK3562:
        case RK3568:
        case RK3576:
@@ -3115,6 +3227,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
        case RK3328:
        case RK3368:
        case RK3399:
+       case RK3528:
        case RK3562:
        case RK3568:
        case RK3576:
@@ -4237,6 +4350,49 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
                .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
 };
 
+static struct rockchip_pin_bank rk3528_pin_banks[] = {
+       PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   0, 0, 0, 0),
+       PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   0x20020, 0x20028, 0x20030, 0x20038),
+       PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   0x30040, 0, 0, 0),
+       PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   0x20060, 0x20068, 0x20070, 0),
+       PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   IOMUX_WIDTH_4BIT,
+                                   0x10080, 0x10088, 0x10090, 0x10098),
+};
+
+static struct rockchip_pin_ctrl rk3528_pin_ctrl = {
+       .pin_banks              = rk3528_pin_banks,
+       .nr_banks               = ARRAY_SIZE(rk3528_pin_banks),
+       .label                  = "RK3528-GPIO",
+       .type                   = RK3528,
+       .pull_calc_reg          = rk3528_calc_pull_reg_and_bit,
+       .drv_calc_reg           = rk3528_calc_drv_reg_and_bit,
+       .schmitt_calc_reg       = rk3528_calc_schmitt_reg_and_bit,
+};
+
 static struct rockchip_pin_bank rk3562_pin_banks[] = {
        PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
                                    IOMUX_WIDTH_4BIT,
@@ -4404,6 +4560,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
                .data = &rk3368_pin_ctrl },
        { .compatible = "rockchip,rk3399-pinctrl",
                .data = &rk3399_pin_ctrl },
+       { .compatible = "rockchip,rk3528-pinctrl",
+               .data = &rk3528_pin_ctrl },
        { .compatible = "rockchip,rk3562-pinctrl",
                .data = &rk3562_pin_ctrl },
        { .compatible = "rockchip,rk3568-pinctrl",

diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index 87a20cec8e21ad2a48dc768f1ec41a5a0d021474..35cd38079d1e76eb0eacc65a64e805103871c3e7 100644 (file)
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -196,6 +196,7 @@ enum rockchip_pinctrl_type {
        RK3328,
        RK3368,
        RK3399,
+       RK3528,
        RK3562,
        RK3568,
        RK3576,