--- /dev/null
+From bec5f70dad45f7ad63f97aa0988821532ebeade7 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Tue, 12 Jul 2016 14:31:23 +0800
+Subject: drm/amd/powerplay: fix the incorrect return value
+
+From: Huang Rui <ray.huang@amd.com>
+
+commit bec5f70dad45f7ad63f97aa0988821532ebeade7 upstream.
+
+The return value 0 (false) means fail to find GPIO in
+atomctrl_get_pp_assign_pin. "-1" returns true as bool actually.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+@@ -592,12 +592,12 @@ bool atomctrl_get_pp_assign_pin(
+ const uint32_t pinId,
+ pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment)
+ {
+- bool bRet = 0;
++ bool bRet = false;
+ ATOM_GPIO_PIN_LUT *gpio_lookup_table =
+ get_gpio_lookup_table(hwmgr->device);
+
+ PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table),
+- "Could not find GPIO lookup Table in BIOS.", return -1);
++ "Could not find GPIO lookup Table in BIOS.", return false);
+
+ bRet = atomctrl_lookup_gpio_pin(gpio_lookup_table, pinId,
+ gpio_pin_assignment);
--- /dev/null
+From a1f5524a66ff6284d1380cdd7723de82698ff9d3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Thu, 28 Jul 2016 17:54:42 +0300
+Subject: drm: aux ->transfer() can return 0, deal with it
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit a1f5524a66ff6284d1380cdd7723de82698ff9d3 upstream.
+
+Restore the correct behaviour (as in check msg.reply) when aux
+->transfer() returns 0. It got removed in
+commit 82922da39190 ("drm/dp_helper: Retry aux transactions on all errors")
+
+Now I can actually dump the "entire" DPCD on a Dell UP2314Q with
+ddrescue. It has some offsets in the DPCD that can't be read
+for some resaon, all you get is defers. Previously ddrescue would
+just give up at the first unredable offset on account of
+read() returning 0 means EOF. Here's the ddrescue log
+for the interested:
+0x00000000 0x00001400 +
+0x00001400 0x00000030 -
+0x00001430 0x000001D0 +
+0x00001600 0x00000030 -
+0x00001630 0x0001F9D0 +
+0x00021000 0x00000001 -
+0x00021001 0x000DEFFF +
+
+Cc: Lyude <cpaul@redhat.com>
+Cc: Daniel Vetter <daniel.vetter@ffwll.ch
+Fixes: 82922da39190 ("drm/dp_helper: Retry aux transactions on all errors")
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/drm_dp_helper.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/drm_dp_helper.c
++++ b/drivers/gpu/drm/drm_dp_helper.c
+@@ -203,7 +203,7 @@ static int drm_dp_dpcd_access(struct drm
+
+ ret = aux->transfer(aux, &msg);
+
+- if (ret > 0) {
++ if (ret >= 0) {
+ native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
+ if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
+ if (ret == size)
--- /dev/null
+From e10aec652f31ec61d6a0b4d00d8ef8d2b66fa0fd Mon Sep 17 00:00:00 2001
+From: Mario Kleiner <mario.kleiner.de@gmail.com>
+Date: Wed, 6 Jul 2016 12:05:44 +0200
+Subject: drm/edid: Add 6 bpc quirk for display AEO model 0.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Mario Kleiner <mario.kleiner.de@gmail.com>
+
+commit e10aec652f31ec61d6a0b4d00d8ef8d2b66fa0fd upstream.
+
+Bugzilla https://bugzilla.kernel.org/show_bug.cgi?id=105331
+reports that the "AEO model 0" display is driven with 8 bpc
+without dithering by default, which looks bad because that
+panel is apparently a 6 bpc DP panel with faulty EDID.
+
+A fix for this was made by commit 013dd9e03872
+("drm/i915/dp: fall back to 18 bpp when sink capability is unknown").
+
+That commit triggers new regressions in precision for DP->DVI and
+DP->VGA displays. A patch is out to revert that commit, but it will
+revert video output for the AEO model 0 panel to 8 bpc without
+dithering.
+
+The EDID 1.3 of that panel, as decoded from the xrandr output
+attached to that bugzilla bug report, is somewhat faulty, and beyond
+other problems also sets the "DFP 1.x compliant TMDS" bit, which
+according to DFP spec means to drive the panel with 8 bpc and
+no dithering in absence of other colorimetry information.
+
+Try to make the original bug reporter happy despite the
+faulty EDID by adding a quirk to mark that panel as 6 bpc,
+so 6 bpc output with dithering creates a nice picture.
+
+Tested by injecting the edid from the fdo bug into a DP connector
+via drm_kms_helper.edid_firmware and verifying the 6 bpc + dithering
+is selected.
+
+This patch should be backported to stable.
+
+Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
+Cc: Jani Nikula <jani.nikula@intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/drm_edid.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/gpu/drm/drm_edid.c
++++ b/drivers/gpu/drm/drm_edid.c
+@@ -74,6 +74,8 @@
+ #define EDID_QUIRK_FORCE_8BPC (1 << 8)
+ /* Force 12bpc */
+ #define EDID_QUIRK_FORCE_12BPC (1 << 9)
++/* Force 6bpc */
++#define EDID_QUIRK_FORCE_6BPC (1 << 10)
+
+ struct detailed_mode_closure {
+ struct drm_connector *connector;
+@@ -100,6 +102,9 @@ static struct edid_quirk {
+ /* Unknown Acer */
+ { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
+
++ /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
++ { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
++
+ /* Belinea 10 15 55 */
+ { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
+ { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
+@@ -4082,6 +4087,9 @@ int drm_add_edid_modes(struct drm_connec
+
+ drm_add_display_info(edid, &connector->display_info, connector);
+
++ if (quirks & EDID_QUIRK_FORCE_6BPC)
++ connector->display_info.bpc = 6;
++
+ if (quirks & EDID_QUIRK_FORCE_8BPC)
+ connector->display_info.bpc = 8;
+
--- /dev/null
+From f15f6ca1e706e11fd07611bd4c7f903625349b33 Mon Sep 17 00:00:00 2001
+From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Date: Wed, 20 Jul 2016 14:26:12 +0300
+Subject: drm/i915/gen9: Add WaInPlaceDecompressionHang
+
+From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+
+commit f15f6ca1e706e11fd07611bd4c7f903625349b33 upstream.
+
+Add this workaround to prevent hang when in place compression
+is used.
+
+References: HSD#2135774
+Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
+Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
+Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+(cherry picked from commit 4ba9c1f7c7b8ca8c1d77f65d408e589dc87b9a2d)
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 2 ++
+ drivers/gpu/drm/i915/i915_reg.h | 3 +++
+ drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++++++++++++++
+ 3 files changed, 19 insertions(+)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -2591,6 +2591,8 @@ struct drm_i915_cmd_table {
+ #define SKL_REVID_D0 0x3
+ #define SKL_REVID_E0 0x4
+ #define SKL_REVID_F0 0x5
++#define SKL_REVID_G0 0x6
++#define SKL_REVID_H0 0x7
+
+ #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -1672,6 +1672,9 @@ enum skl_disp_power_wells {
+
+ #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
+
++#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
++#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
++
+ #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
+ #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
+
+--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
+@@ -1135,6 +1135,11 @@ static int skl_init_workarounds(struct i
+ /* WaDisableGafsUnitClkGating:skl */
+ WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+
++ /* WaInPlaceDecompressionHang:skl */
++ if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
++ WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
++ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
++
+ /* WaDisableLSQCROPERFforOCL:skl */
+ ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
+ if (ret)
+@@ -1194,6 +1199,11 @@ static int bxt_init_workarounds(struct i
+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
++ /* WaInPlaceDecompressionHang:bxt */
++ if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
++ WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
++ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
++
+ return 0;
+ }
+
+@@ -1241,6 +1251,10 @@ static int kbl_init_workarounds(struct i
+ GEN7_HALF_SLICE_CHICKEN1,
+ GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+
++ /* WaInPlaceDecompressionHang:kbl */
++ WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
++ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
++
+ /* WaDisableLSQCROPERFforOCL:kbl */
+ ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
+ if (ret)
--- /dev/null
+From 7f1052a8fa38df635ab0dc0e6025b64ab9834824 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Tue, 26 Apr 2016 19:46:32 +0300
+Subject: drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 7f1052a8fa38df635ab0dc0e6025b64ab9834824 upstream.
+
+Update CDCLK_FREQ on BDW after changing the cdclk frequency. Not sure
+if this is a late addition to the spec, or if I simply overlooked this
+step when writing the original code.
+
+This is what Bspec has to say about CDCLK_FREQ:
+"Program this field to the CD clock frequency minus one. This is used to
+ generate a divided down clock for miscellaneous timers in display."
+
+And the "Broadwell Sequences for Changing CD Clock Frequency" section
+clarifies this further:
+"For CD clock 337.5 MHz, program 337 decimal.
+ For CD clock 450 MHz, program 449 decimal.
+ For CD clock 540 MHz, program 539 decimal.
+ For CD clock 675 MHz, program 674 decimal."
+
+Cc: Mika Kahola <mika.kahola@intel.com>
+Fixes: b432e5cfd5e9 ("drm/i915: BDW clock change support")
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.com
+Reviewed-by: Mika Kahola <mika.kahola@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_reg.h | 2 ++
+ drivers/gpu/drm/i915/intel_display.c | 2 ++
+ 2 files changed, 4 insertions(+)
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -7538,6 +7538,8 @@ enum skl_disp_power_wells {
+
+ #define CDCLK_FREQ _MMIO(0x46200)
+
++#define CDCLK_FREQ _MMIO(0x46200)
++
+ #define _TRANSA_MSA_MISC 0x60410
+ #define _TRANSB_MSA_MISC 0x61410
+ #define _TRANSC_MSA_MISC 0x62410
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -9700,6 +9700,8 @@ static void broadwell_set_cdclk(struct d
+
+ I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
+
++ I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
++
+ intel_update_cdclk(dev);
+
+ WARN(cdclk != dev_priv->cdclk_freq,
--- /dev/null
+From 0e67bed2c765ff0fdaec62c963881f5416fe3692 Mon Sep 17 00:00:00 2001
+From: Ben Skeggs <bskeggs@redhat.com>
+Date: Tue, 12 Jul 2016 11:57:07 +1000
+Subject: drm/nouveau: check for supported chipset before booting fbdev off the hw
+
+From: Ben Skeggs <bskeggs@redhat.com>
+
+commit 0e67bed2c765ff0fdaec62c963881f5416fe3692 upstream.
+
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/nouveau/nouveau_drm.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
++++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
+@@ -324,7 +324,16 @@ static int nouveau_drm_probe(struct pci_
+ !vga_switcheroo_handler_flags())
+ return -EPROBE_DEFER;
+
+- /* remove conflicting drivers (vesafb, efifb etc) */
++ /* We need to check that the chipset is supported before booting
++ * fbdev off the hardware, as there's no way to put it back.
++ */
++ ret = nvkm_device_pci_new(pdev, NULL, "error", true, false, 0, &device);
++ if (ret)
++ return ret;
++
++ nvkm_device_del(&device);
++
++ /* Remove conflicting drivers (vesafb, efifb etc). */
+ aper = alloc_apertures(3);
+ if (!aper)
+ return -ENOMEM;
--- /dev/null
+From 28668f43b8e421634e1623f72a879812288dd06b Mon Sep 17 00:00:00 2001
+From: Mikulas Patocka <mpatocka@redhat.com>
+Date: Thu, 28 Jul 2016 18:56:13 -0400
+Subject: drm/nouveau/fbcon: fix font width not divisible by 8
+
+From: Mikulas Patocka <mpatocka@redhat.com>
+
+commit 28668f43b8e421634e1623f72a879812288dd06b upstream.
+
+The patch f045f459d925 ("drm/nouveau/fbcon: fix out-of-bounds memory accesses")
+tries to fix some out of memory accesses. Unfortunatelly, the patch breaks the
+display when using fonts with width that is not divisiable by 8.
+
+The monochrome bitmap for each character is stored in memory by lines from top
+to bottom. Each line is padded to a full byte.
+
+For example, for 22x11 font, each line is padded to 16 bits, so each
+character is consuming 44 bytes total, that is 11 32-bit words. The patch
+f045f459d925 changed the logic to "dsize = ALIGN(image->width *
+image->height, 32) >> 5", that is just 8 words - this is incorrect and it
+causes display corruption.
+
+This patch adds the necesary padding of lines to 8 bytes.
+
+This patch should be backported to stable kernels where f045f459d925 was
+backported.
+
+Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
+Fixes: f045f459d925 ("drm/nouveau/fbcon: fix out-of-bounds memory accesses")
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/nouveau/nv04_fbcon.c | 4 ++--
+ drivers/gpu/drm/nouveau/nv50_fbcon.c | 2 +-
+ drivers/gpu/drm/nouveau/nvc0_fbcon.c | 2 +-
+ 3 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c
++++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c
+@@ -107,11 +107,11 @@ nv04_fbcon_imageblit(struct fb_info *inf
+ ((image->dx + image->width) & 0xffff));
+ OUT_RING(chan, bg);
+ OUT_RING(chan, fg);
+- OUT_RING(chan, (image->height << 16) | image->width);
++ OUT_RING(chan, (image->height << 16) | ALIGN(image->width, 8));
+ OUT_RING(chan, (image->height << 16) | image->width);
+ OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
+
+- dsize = ALIGN(image->width * image->height, 32) >> 5;
++ dsize = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5;
+ while (dsize) {
+ int iter_len = dsize > 128 ? 128 : dsize;
+
+--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c
++++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c
+@@ -125,7 +125,7 @@ nv50_fbcon_imageblit(struct fb_info *inf
+ OUT_RING(chan, 0);
+ OUT_RING(chan, image->dy);
+
+- dwords = ALIGN(image->width * image->height, 32) >> 5;
++ dwords = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5;
+ while (dwords) {
+ int push = dwords > 2047 ? 2047 : dwords;
+
+--- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c
++++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c
+@@ -125,7 +125,7 @@ nvc0_fbcon_imageblit(struct fb_info *inf
+ OUT_RING (chan, 0);
+ OUT_RING (chan, image->dy);
+
+- dwords = ALIGN(image->width * image->height, 32) >> 5;
++ dwords = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5;
+ while (dwords) {
+ int push = dwords > 2047 ? 2047 : dwords;
+
--- /dev/null
+From d0e62ef6ed257715a88d0e5d7cd850a1695429e2 Mon Sep 17 00:00:00 2001
+From: Ilia Mirkin <imirkin@alum.mit.edu>
+Date: Wed, 27 Jul 2016 19:16:39 -0400
+Subject: drm/nouveau/gr/nv3x: fix instobj write offsets in gr setup
+
+From: Ilia Mirkin <imirkin@alum.mit.edu>
+
+commit d0e62ef6ed257715a88d0e5d7cd850a1695429e2 upstream.
+
+This should fix some unaligned access warnings. This is also likely to
+fix non-descript issues on nv30/nv34 as a result of incorrect channel
+setup.
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96836
+Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 4 ++--
+ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
++++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
+@@ -76,8 +76,8 @@ nv30_gr_chan_new(struct nvkm_gr *base, s
+ nvkm_wo32(chan->inst, i, 0x00040004);
+ for (i = 0x1f18; i <= 0x3088 ; i += 16) {
+ nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
+- nvkm_wo32(chan->inst, i + 1, 0x0436086c);
+- nvkm_wo32(chan->inst, i + 2, 0x000c001b);
++ nvkm_wo32(chan->inst, i + 4, 0x0436086c);
++ nvkm_wo32(chan->inst, i + 8, 0x000c001b);
+ }
+ for (i = 0x30b8; i < 0x30c8; i += 4)
+ nvkm_wo32(chan->inst, i, 0x0000ffff);
+--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
++++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
+@@ -75,8 +75,8 @@ nv34_gr_chan_new(struct nvkm_gr *base, s
+ nvkm_wo32(chan->inst, i, 0x00040004);
+ for (i = 0x15ac; i <= 0x271c ; i += 16) {
+ nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
+- nvkm_wo32(chan->inst, i + 1, 0x0436086c);
+- nvkm_wo32(chan->inst, i + 2, 0x000c001b);
++ nvkm_wo32(chan->inst, i + 4, 0x0436086c);
++ nvkm_wo32(chan->inst, i + 8, 0x000c001b);
+ }
+ for (i = 0x274c; i < 0x275c; i += 4)
+ nvkm_wo32(chan->inst, i, 0x0000ffff);
--- /dev/null
+From 396f5d62d1a5fd99421855a08ffdef8edb43c76e Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Thu, 7 Jul 2016 09:41:12 +0100
+Subject: drm: Restore double clflush on the last partial cacheline
+
+From: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit 396f5d62d1a5fd99421855a08ffdef8edb43c76e upstream.
+
+This effectively reverts
+
+commit afcd950cafea6e27b739fe7772cbbeed37d05b8b
+Author: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Wed Jun 10 15:58:01 2015 +0100
+
+ drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()
+
+as we have observed issues with serialisation of the clflush operations
+on Baytrail+ Atoms with partial updates. Applying the double flush on the
+last cacheline forces that clflush to be ordered with respect to the
+previous clflush, and the mfence then protects against prefetches crossing
+the clflush boundary.
+
+The same issue can be demonstrated in userspace with igt/gem_exec_flush.
+
+Fixes: afcd950cafea6 (drm: Avoid the double clflush on the last cache...)
+Testcase: igt/gem_concurrent_blit
+Testcase: igt/gem_partial_pread_pwrite
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: dri-devel@lists.freedesktop.org
+Cc: Akash Goel <akash.goel@intel.com>
+Cc: Imre Deak <imre.deak@intel.com>
+Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
+Cc: Jason Ekstrand <jason.ekstrand@intel.com>
+Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: http://patchwork.freedesktop.org/patch/msgid/1467880930-23082-6-git-send-email-chris@chris-wilson.co.uk
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/drm_cache.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/drm_cache.c
++++ b/drivers/gpu/drm/drm_cache.c
+@@ -136,6 +136,7 @@ drm_clflush_virt_range(void *addr, unsig
+ mb();
+ for (; addr < end; addr += size)
+ clflushopt(addr);
++ clflushopt(end - 1); /* force serialisation */
+ mb();
+ return;
+ }
--- /dev/null
+From dc0b408f5a87cce3ea3f81a6800244fb7d395435 Mon Sep 17 00:00:00 2001
+From: John Keeping <john@metanate.com>
+Date: Thu, 14 Jul 2016 16:29:15 +0100
+Subject: drm/rockchip: allocate correct crtc state structure on reset
+
+From: John Keeping <john@metanate.com>
+
+commit dc0b408f5a87cce3ea3f81a6800244fb7d395435 upstream.
+
+Because we are using a custom crtc_state structure, we must override the
+reset helper to allocate the correct amount of memory.
+
+Fixes: 4e257d9eee23 ("drm/rockchip: get rid of rockchip_drm_crtc_mode_config")
+Signed-off-by: John Keeping <john@metanate.com>
+Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
+Reviewed-by: Sean Paul <seanpaul@chromium.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1048,6 +1048,17 @@ static void vop_crtc_destroy(struct drm_
+ drm_crtc_cleanup(crtc);
+ }
+
++static void vop_crtc_reset(struct drm_crtc *crtc)
++{
++ if (crtc->state)
++ __drm_atomic_helper_crtc_destroy_state(crtc->state);
++ kfree(crtc->state);
++
++ crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
++ if (crtc->state)
++ crtc->state->crtc = crtc;
++}
++
+ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
+ {
+ struct rockchip_crtc_state *rockchip_state;
+@@ -1073,7 +1084,7 @@ static const struct drm_crtc_funcs vop_c
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .destroy = vop_crtc_destroy,
+- .reset = drm_atomic_helper_crtc_reset,
++ .reset = vop_crtc_reset,
+ .atomic_duplicate_state = vop_crtc_duplicate_state,
+ .atomic_destroy_state = vop_crtc_destroy_state,
+ };
drm-radeon-poll-for-both-connect-disconnect-on-analog-connectors.patch
drm-radeon-fix-firmware-info-version-checks.patch
drm-radeon-support-backlight-control-for-uniphy3.patch
+drm-nouveau-check-for-supported-chipset-before-booting-fbdev-off-the-hw.patch
+drm-nouveau-gr-nv3x-fix-instobj-write-offsets-in-gr-setup.patch
+drm-nouveau-fbcon-fix-font-width-not-divisible-by-8.patch
+drm-restore-double-clflush-on-the-last-partial-cacheline.patch
+drm-i915-update-cdclk_freq-register-on-bdw-after-changing-cdclk-frequency.patch
+drm-amd-powerplay-fix-the-incorrect-return-value.patch
+drm-rockchip-allocate-correct-crtc-state-structure-on-reset.patch
+drm-i915-gen9-add-wainplacedecompressionhang.patch
+drm-aux-transfer-can-return-0-deal-with-it.patch
+drm-edid-add-6-bpc-quirk-for-display-aeo-model-0.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
