]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
genirq: Provide IRQCHIP_MOVE_DEFERRED
authorThomas Gleixner <tglx@linutronix.de>
Tue, 10 Dec 2024 10:34:14 +0000 (11:34 +0100)
committerThomas Gleixner <tglx@linutronix.de>
Wed, 15 Jan 2025 09:56:22 +0000 (10:56 +0100)
The logic of GENERIC_PENDING_IRQ is backwards for historical reasons. Most
interrupt controllers allow to move the interrupt from arbitrary
contexts. If GENERIC_PENDING_IRQ is enabled by an architecture to support a
chip, which requires the affinity change to happen in interrupt context,
all other chips have to be marked with IRQF_MOVE_PCNTXT.

That's tedious and there is no real good reason for the extra flags in the
irq descriptor and the irq data status fields. In fact the decision whether
interrupts can be moved in arbitrary context or not is a property of the
interrupt chip.

To simplify adoption for RISC-V provide a new mechanism which is enabled
via a config switch and allows to add a flag to irq_chip::flags to request
that interrupt affinity changes are deferred. Setting the top level chip of
an interrupt evaluates the flag and maps it into the existing logic.

The config switch and the various PCNTXT flags are temporary until x86 is
converted over to this scheme. This intermediate step also allows trivial
backporting of the mechanism to plug the affinity change race of various
RISC-V interrupt controllers.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20241210103335.500314436@linutronix.de
include/linux/irq.h
kernel/irq/Kconfig
kernel/irq/chip.c
kernel/irq/debugfs.c

index 25f51bf3c351f9652d39a9c4ff61ebe3e789e6ed..6e021548fa0a414ba7d1e73b1029500e628b71ef 100644 (file)
@@ -567,6 +567,7 @@ struct irq_chip {
  *                                    in the suspend path if they are in disabled state
  * IRQCHIP_AFFINITY_PRE_STARTUP:      Default affinity update before startup
  * IRQCHIP_IMMUTABLE:                Don't ever change anything in this chip
+ * IRQCHIP_MOVE_DEFERRED:            Move the interrupt in actual interrupt context
  */
 enum {
        IRQCHIP_SET_TYPE_MASKED                 = (1 <<  0),
@@ -581,6 +582,7 @@ enum {
        IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND        = (1 <<  9),
        IRQCHIP_AFFINITY_PRE_STARTUP            = (1 << 10),
        IRQCHIP_IMMUTABLE                       = (1 << 11),
+       IRQCHIP_MOVE_DEFERRED                   = (1 << 12),
 };
 
 #include <linux/irqdesc.h>
index 875f25ed6f710aa002b7af7870cdc32fa06dd92b..5432418c0feafbf58e88ba6d0f88a28ccda9ebeb 100644 (file)
@@ -31,6 +31,10 @@ config GENERIC_IRQ_EFFECTIVE_AFF_MASK
 config GENERIC_PENDING_IRQ
        bool
 
+# Deduce delayed migration from top-level interrupt chip flags
+config GENERIC_PENDING_IRQ_CHIPFLAGS
+       bool
+
 # Support for generic irq migrating off cpu before the cpu is offline.
 config GENERIC_IRQ_MIGRATION
        bool
index 271e9139de77f5348539c95e3463c4fb7585df10..7989da287d4ca1a531eb7e15d20840c7f07e279c 100644 (file)
@@ -47,6 +47,13 @@ int irq_set_chip(unsigned int irq, const struct irq_chip *chip)
                return -EINVAL;
 
        desc->irq_data.chip = (struct irq_chip *)(chip ?: &no_irq_chip);
+
+       if (IS_ENABLED(CONFIG_GENERIC_PENDING_IRQ_CHIPFLAGS) && chip) {
+               if (chip->flags & IRQCHIP_MOVE_DEFERRED)
+                       irqd_clear(&desc->irq_data, IRQD_MOVE_PCNTXT);
+               else
+                       irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
+       }
        irq_put_desc_unlock(desc, flags);
        /*
         * For !CONFIG_SPARSE_IRQ make the irq show up in
@@ -1114,16 +1121,21 @@ void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
        trigger = irqd_get_trigger_type(&desc->irq_data);
 
        irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
-                  IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
+                  IRQD_TRIGGER_MASK | IRQD_LEVEL);
        if (irq_settings_has_no_balance_set(desc))
                irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
        if (irq_settings_is_per_cpu(desc))
                irqd_set(&desc->irq_data, IRQD_PER_CPU);
-       if (irq_settings_can_move_pcntxt(desc))
-               irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
        if (irq_settings_is_level(desc))
                irqd_set(&desc->irq_data, IRQD_LEVEL);
 
+       /* Keep this around until x86 is converted over */
+       if (!IS_ENABLED(CONFIG_GENERIC_PENDING_IRQ_CHIPFLAGS)) {
+               irqd_clear(&desc->irq_data, IRQD_MOVE_PCNTXT);
+               if (irq_settings_can_move_pcntxt(desc))
+                       irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
+       }
+
        tmp = irq_settings_get_trigger_mask(desc);
        if (tmp != IRQ_TYPE_NONE)
                trigger = tmp;
index c6ffb97966bed4b91e581b086cd3ac35c3987f26..975eb8d681682cfa4743545ab0f477d14ee7396d 100644 (file)
@@ -53,6 +53,7 @@ static const struct irq_bit_descr irqchip_flags[] = {
        BIT_MASK_DESCR(IRQCHIP_SUPPORTS_NMI),
        BIT_MASK_DESCR(IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND),
        BIT_MASK_DESCR(IRQCHIP_IMMUTABLE),
+       BIT_MASK_DESCR(IRQCHIP_MOVE_DEFERRED),
 };
 
 static void