--- /dev/null
+From a1216444283e81fd904593a4a77c90adfe5d14d1 Mon Sep 17 00:00:00 2001
+From: Paulo Zanoni <paulo.r.zanoni@intel.com>
+Date: Thu, 21 Nov 2013 13:47:16 -0200
+Subject: drm/i915: use the correct force_wake function at the PC8 code
+
+From: Paulo Zanoni <paulo.r.zanoni@intel.com>
+
+commit a1216444283e81fd904593a4a77c90adfe5d14d1 upstream.
+
+When I submitted the first patch adding these force wake functions,
+Chris Wilson observed that I was using the wrong functions, so I sent
+a second version of the patch to correct this problem. The problem is
+that v1 was merged instead of v2.
+
+I was able to notice the problem when running the
+debugfs-forcewake-user subtest of pm_pc8 from intel-gpu-tools.
+
+Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
+Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_display.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -6062,7 +6062,7 @@ void hsw_restore_lcpll(struct drm_i915_p
+
+ /* Make sure we're not on PC8 state before disabling PC8, otherwise
+ * we'll hang the machine! */
+- dev_priv->uncore.funcs.force_wake_get(dev_priv);
++ gen6_gt_force_wake_get(dev_priv);
+
+ if (val & LCPLL_POWER_DOWN_ALLOW) {
+ val &= ~LCPLL_POWER_DOWN_ALLOW;
+@@ -6093,7 +6093,7 @@ void hsw_restore_lcpll(struct drm_i915_p
+ DRM_ERROR("Switching back to LCPLL failed\n");
+ }
+
+- dev_priv->uncore.funcs.force_wake_put(dev_priv);
++ gen6_gt_force_wake_put(dev_priv);
+ }
+
+ void hsw_enable_pc8_work(struct work_struct *__work)
--- /dev/null
+From ffd3d3361d583cb73fa65a5fed3a196ba6f261bb Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 3 Dec 2013 17:16:49 -0500
+Subject: drm/radeon/atom: fix bus probes when hw_i2c is set (v2)
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit ffd3d3361d583cb73fa65a5fed3a196ba6f261bb upstream.
+
+When probing the bus, we need to set the byte count
+to 0 rather than 1.
+
+v2: Don't count the first byte.
+
+bug:
+https://bugzilla.kernel.org/show_bug.cgi?id=66241
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atombios_i2c.c | 15 +++++++++------
+ 1 file changed, 9 insertions(+), 6 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_i2c.c
++++ b/drivers/gpu/drm/radeon/atombios_i2c.c
+@@ -44,7 +44,7 @@ static int radeon_process_i2c_ch(struct
+ PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
+ int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
+ unsigned char *base;
+- u16 out;
++ u16 out = cpu_to_le16(0);
+
+ memset(&args, 0, sizeof(args));
+
+@@ -55,11 +55,14 @@ static int radeon_process_i2c_ch(struct
+ DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 3)\n", num);
+ return -EINVAL;
+ }
+- args.ucRegIndex = buf[0];
+- if (num > 1) {
++ if (buf == NULL)
++ args.ucRegIndex = 0;
++ else
++ args.ucRegIndex = buf[0];
++ if (num)
+ num--;
++ if (num)
+ memcpy(&out, &buf[1], num);
+- }
+ args.lpI2CDataOut = cpu_to_le16(out);
+ } else {
+ if (num > ATOM_MAX_HW_I2C_READ) {
+@@ -96,14 +99,14 @@ int radeon_atom_hw_i2c_xfer(struct i2c_a
+ struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
+ struct i2c_msg *p;
+ int i, remaining, current_count, buffer_offset, max_bytes, ret;
+- u8 buf = 0, flags;
++ u8 flags;
+
+ /* check for bus probe */
+ p = &msgs[0];
+ if ((num == 1) && (p->len == 0)) {
+ ret = radeon_process_i2c_ch(i2c,
+ p->addr, HW_I2C_WRITE,
+- &buf, 1);
++ NULL, 0);
+ if (ret)
+ return ret;
+ else
--- /dev/null
+From 180f805f4f03b2894701f9831b4e96a308330b22 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 21 Nov 2013 09:52:01 -0500
+Subject: drm/radeon: fix typo in fetching mpll params
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 180f805f4f03b2894701f9831b4e96a308330b22 upstream.
+
+Copy-paste typo. Value should be 0-2, not 0-1.
+
+Noticed-by: Sylvain BERTRAND <sylware@legeek.net>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_atombios.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -2918,7 +2918,7 @@ int radeon_atom_get_memory_pll_dividers(
+ mpll_param->dll_speed = args.ucDllSpeed;
+ mpll_param->bwcntl = args.ucBWCntl;
+ mpll_param->vco_mode =
+- (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK) ? 1 : 0;
++ (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
+ mpll_param->yclk_sel =
+ (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
+ mpll_param->qdr =
--- /dev/null
+From 0ca223b029a261e82fb2f50c52eb85d510f4260e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 3 Dec 2013 09:24:30 -0500
+Subject: drm/radeon: fixup bad vram size on SI
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 0ca223b029a261e82fb2f50c52eb85d510f4260e upstream.
+
+Some boards seem to have garbage in the upper
+16 bits of the vram size register. Check for
+this and clamp the size properly. Fixes
+boards reporting bogus amounts of vram.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/si.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/si.c
++++ b/drivers/gpu/drm/radeon/si.c
+@@ -3887,8 +3887,15 @@ static int si_mc_init(struct radeon_devi
+ rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
+ rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
+ /* size in MB on si */
+- rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
+- rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
++ tmp = RREG32(CONFIG_MEMSIZE);
++ /* some boards may have garbage in the upper 16 bits */
++ if (tmp & 0xffff0000) {
++ DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
++ if (tmp & 0xffff)
++ tmp &= 0xffff;
++ }
++ rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;
++ rdev->mc.real_vram_size = rdev->mc.mc_vram_size;
+ rdev->mc.visible_vram_size = rdev->mc.aper_size;
+ si_vram_gtt_location(rdev, &rdev->mc);
+ radeon_update_bandwidth_info(rdev);
--- /dev/null
+From 55d4e020fb8ddd3896a8cd3351028f5c3a2c4bd3 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 25 Nov 2013 13:20:59 -0500
+Subject: drm/radeon: program DCE2 audio dto just like DCE3
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 55d4e020fb8ddd3896a8cd3351028f5c3a2c4bd3 upstream.
+
+Seems to work like the DCE3 version despite what
+the register spec says.
+
+bug:
+https://bugs.freedesktop.org/show_bug.cgi?id=71975
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/r600_hdmi.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/r600_hdmi.c
++++ b/drivers/gpu/drm/radeon/r600_hdmi.c
+@@ -304,9 +304,9 @@ void r600_audio_set_dto(struct drm_encod
+ WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
+ WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
+ }
+- } else if (ASIC_IS_DCE3(rdev)) {
++ } else {
+ /* according to the reg specs, this should DCE3.2 only, but in
+- * practice it seems to cover DCE3.0/3.1 as well.
++ * practice it seems to cover DCE2.0/3.0/3.1 as well.
+ */
+ if (dig->dig_encoder == 0) {
+ WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
+@@ -317,10 +317,6 @@ void r600_audio_set_dto(struct drm_encod
+ WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
+ WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
+ }
+- } else {
+- /* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */
+- WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
+- AUDIO_DTO_MODULE(clock / 10));
+ }
+ }
+
mwifiex-fix-memory-leak-issue-for-ibss-join.patch
net-allwinner-emac-add-missing-free_irq.patch
igb-fix-for-issue-where-values-could-be-too-high-for-udelay-function.patch
+drm-i915-use-the-correct-force_wake-function-at-the-pc8-code.patch
+drm-radeon-fix-typo-in-fetching-mpll-params.patch
+drm-radeon-program-dce2-audio-dto-just-like-dce3.patch
+drm-radeon-fixup-bad-vram-size-on-si.patch
+drm-radeon-atom-fix-bus-probes-when-hw_i2c-is-set-v2.patch
+x86-efi-don-t-use-u-efi-time-services-on-32-bit.patch
--- /dev/null
+From 04bf9ba720fcc4fa313fa122b799ae0989b6cd50 Mon Sep 17 00:00:00 2001
+From: Matthew Garrett <matthew.garrett@nebula.com>
+Date: Fri, 29 Nov 2013 14:44:43 -0500
+Subject: x86, efi: Don't use (U)EFI time services on 32 bit
+
+From: Matthew Garrett <matthew.garrett@nebula.com>
+
+commit 04bf9ba720fcc4fa313fa122b799ae0989b6cd50 upstream.
+
+UEFI time services are often broken once we're in virtual mode. We were
+already refusing to use them on 64-bit systems, but it turns out that
+they're also broken on some 32-bit firmware, including the Dell Venue.
+Disable them for now, we can revisit once we have the 1:1 mappings code
+incorporated.
+
+Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com>
+Link: http://lkml.kernel.org/r/1385754283-2464-1-git-send-email-matthew.garrett@nebula.com
+Cc: Matt Fleming <matt.fleming@intel.com>
+Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/platform/efi/efi.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+--- a/arch/x86/platform/efi/efi.c
++++ b/arch/x86/platform/efi/efi.c
+@@ -768,13 +768,6 @@ void __init efi_init(void)
+
+ set_bit(EFI_MEMMAP, &x86_efi_facility);
+
+-#ifdef CONFIG_X86_32
+- if (efi_is_native()) {
+- x86_platform.get_wallclock = efi_get_time;
+- x86_platform.set_wallclock = efi_set_rtc_mmss;
+- }
+-#endif
+-
+ #if EFI_DEBUG
+ print_efi_memmap();
+ #endif
projects / thirdparty / kernel / stable-queue.git / commitdiff
