drm/i915/display: Prepare for dsc 3 stream splitter

At the moment dsc_split represents whether the dsc splitter is used
or not. With 3 DSC engines, the splitter can split into two streams
or three streams.

Instead of representing the splitter's state, it is more effective to
represent the number of DSC streams per pipe.

Replace the `dsc.dsc_split` member with `dsc.num_streams` to indicate the
number of DSC streams used per pipe. This change will implicitly
convey the splitter's operation mode.

v2: Avoid new enum for dsc split. (Suraj)
v3:
-Replace dsc_split with num_stream. (Suraj)
-Avoid extra parentheses. (Jani)
v4: Set num_streams to 1, if VDSC_JOINER not set while readout.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-3-ankit.k.nautiyal@intel.com

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 8a49f499e3fb3fffa2ee03b2504daad5d3941318..74ab3d1a16227a5a46dd2df1b19a0abba7baa7c4 100644 (file)
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1602,7 +1602,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 
        /* FIXME: split only when necessary */
        if (crtc_state->dsc.slice_count > 1)
-               crtc_state->dsc.dsc_split = true;
+               crtc_state->dsc.num_streams = 2;
+       else
+               crtc_state->dsc.num_streams = 1;
 
        /* FIXME: initialize from VBT */
        vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 863927f429aa7344c52599ba34f421c5d565e737..d7f92dc56d1e965c9612289ecf034177a43d2390 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5743,7 +5743,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
        PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
 
        PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
-       PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
+       PIPE_CONF_CHECK_I(dsc.num_streams);
        PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
 
        PIPE_CONF_CHECK_BOOL(splitter.enable);

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ff6eb93337e0a834d0a87e186b698f93c133f1bc..d3a1aa7c919f4b1cfe4b787d2813e850b224bd9b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1235,7 +1235,7 @@ struct intel_crtc_state {
        /* Display Stream compression state */
        struct {
                bool compression_enable;
-               bool dsc_split;
+               int num_streams;
                /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
                u16 compressed_bpp_x16;
                u8 slice_count;

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 55eb1e55a94d1bb9bf5a927aa8d32b4ce080128c..5b120d3ad23dd5e7e821c9004a202695bb7b588f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2413,7 +2413,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
         * then we need to use 2 VDSC instances.
         */
        if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
-               pipe_config->dsc.dsc_split = true;
+               pipe_config->dsc.num_streams = 2;
+       else
+               pipe_config->dsc.num_streams = 1;
 
        ret = intel_dp_dsc_compute_params(connector, pipe_config);
        if (ret < 0) {

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 40525f5c4c4290e086ffa4422a61c97efe20cec4..168f39499c666d15eb006094db40341b8a997c48 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -379,7 +379,7 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 
 static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
 {
-       return crtc_state->dsc.dsc_split ? 2 : 1;
+       return crtc_state->dsc.num_streams;
 }
 
 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
@@ -976,8 +976,10 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
        if (!crtc_state->dsc.compression_enable)
                goto out;
 
-       crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
-               (dss_ctl1 & JOINER_ENABLE);
+       if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE)
+               crtc_state->dsc.num_streams = 2;
+       else
+               crtc_state->dsc.num_streams = 1;
 
        intel_dsc_get_pps_config(crtc_state);
 out:
@@ -988,10 +990,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
                                  const struct intel_crtc_state *crtc_state)
 {
        drm_printf_indent(p, indent,
-                         "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n",
+                         "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n",
                          FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
                          crtc_state->dsc.slice_count,
-                         str_yes_no(crtc_state->dsc.dsc_split));
+                         crtc_state->dsc.num_streams);
 }
 
 void intel_vdsc_state_dump(struct drm_printer *p, int indent,