LoongArch: Don't panic if no valid cache info for PCI

If there is no valid cache info detected (may happen in virtual machine)
for pci_dfl_cache_line_size, kernel shouldn't panic. Because in the PCI
core it will be evaluated to (L1_CACHE_BYTES >> 2).

Cc: <stable@vger.kernel.org>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

diff --git a/arch/loongarch/pci/pci.c b/arch/loongarch/pci/pci.c
index 5bc9627a6cf9cbb7f454f8fb8b418a4f7d3c827b..d9fc5d520b3778b6cc2d088d1b0713a8bb2504b3 100644 (file)
--- a/arch/loongarch/pci/pci.c
+++ b/arch/loongarch/pci/pci.c
@@ -50,11 +50,11 @@ static int __init pcibios_init(void)
         */
        lsize = cpu_last_level_cache_line_size();
 
-       BUG_ON(!lsize);
+       if (lsize) {
+               pci_dfl_cache_line_size = lsize >> 2;
 
-       pci_dfl_cache_line_size = lsize >> 2;
-
-       pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
+               pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
+       }
 
        return 0;
 }