riscv: dts: spacemit: Add clock tree for SpacemiT K1

Describe the PLL and system controllers that're capable of generating
clock signals in the devicetree.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250508111528.10508-2-heylenay@4d2.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>

diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index c670ebf8fa12917aa6493fcd89fdd1409529538b..85c9730dd082a46ec575a760d30558803b5ccba3 100644 (file)
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
  */
 
+#include <dt-bindings/clock/spacemit,k1-syscon.h>
+
 /dts-v1/;
 / {
        #address-cells = <2>;
@@ -306,6 +308,36 @@
                };
        };
 
+       clocks {
+               vctcxo_1m: clock-1m {
+                       compatible = "fixed-clock";
+                       clock-frequency = <1000000>;
+                       clock-output-names = "vctcxo_1m";
+                       #clock-cells = <0>;
+               };
+
+               vctcxo_24m: clock-24m {
+                       compatible = "fixed-clock";
+                       clock-frequency = <24000000>;
+                       clock-output-names = "vctcxo_24m";
+                       #clock-cells = <0>;
+               };
+
+               vctcxo_3m: clock-3m {
+                       compatible = "fixed-clock";
+                       clock-frequency = <3000000>;
+                       clock-output-names = "vctcxo_3m";
+                       #clock-cells = <0>;
+               };
+
+               osc_32k: clock-32k {
+                       compatible = "fixed-clock";
+                       clock-frequency = <32000>;
+                       clock-output-names = "osc_32k";
+                       #clock-cells = <0>;
+               };
+       };
+
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&plic>;
@@ -314,6 +346,17 @@
                dma-noncoherent;
                ranges;
 
+               syscon_apbc: system-controller@d4015000 {
+                       compatible = "spacemit,k1-syscon-apbc";
+                       reg = <0x0 0xd4015000 0x0 0x1000>;
+                       clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
+                                <&vctcxo_24m>;
+                       clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
+                                     "vctcxo_24m";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
                uart0: serial@d4017000 {
                        compatible = "spacemit,k1-uart", "intel,xscale-uart";
                        reg = <0x0 0xd4017000 0x0 0x100>;
@@ -409,6 +452,38 @@
                        reg = <0x0 0xd401e000 0x0 0x400>;
                };
 
+               syscon_mpmu: system-controller@d4050000 {
+                       compatible = "spacemit,k1-syscon-mpmu";
+                       reg = <0x0 0xd4050000 0x0 0x209c>;
+                       clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
+                                <&vctcxo_24m>;
+                       clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
+                                     "vctcxo_24m";
+                       #clock-cells = <1>;
+                       #power-domain-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               pll: clock-controller@d4090000 {
+                       compatible = "spacemit,k1-pll";
+                       reg = <0x0 0xd4090000 0x0 0x1000>;
+                       clocks = <&vctcxo_24m>;
+                       spacemit,mpmu = <&syscon_mpmu>;
+                       #clock-cells = <1>;
+               };
+
+               syscon_apmu: system-controller@d4282800 {
+                       compatible = "spacemit,k1-syscon-apmu";
+                       reg = <0x0 0xd4282800 0x0 0x400>;
+                       clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
+                                <&vctcxo_24m>;
+                       clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
+                                     "vctcxo_24m";
+                       #clock-cells = <1>;
+                       #power-domain-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
                plic: interrupt-controller@e0000000 {
                        compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
                        reg = <0x0 0xe0000000 0x0 0x4000000>;