i386: Avoid integer logic insns for 32bit and 64bit vector modes [PR100701]

Integer logic instructions clobber flags, do not use them for
32bit and 64bit vector modes.

2021-05-20  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
	PR target/100701
	* config/i386/i386.md (isa): Remove x64_bmi.
	(enabled): Remove x64_bmi.
	* config/i386/mmx.md (mmx_andnot<MMXMODEI:mode>3):
	Remove general register alternative.
	(*andnot<VI_32:mode>3): Ditto.
	(*mmx_<any_logic:code><MMXMODEI:mode>3): Ditto.
	(*<any_logic:code><VI_32:mode>3): Ditto.

gcc/testsuite/

	PR target/100701
	* gcc.target/i386/pr100701.c: New test.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2fc8fae30f310b59f67e23c4f59f49be94d8369e..960ecbd327a73fb1291a0ec49200b58b587747b2 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -815,7 +815,7 @@
 (define_attr "movu" "0,1" (const_string "0"))
 
 ;; Used to control the "enabled" attribute on a per-instruction basis.
-(define_attr "isa" "base,x64,nox64,x64_bmi,x64_sse2,x64_sse4,x64_sse4_noavx,
+(define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx,
                    x64_avx,x64_avx512bw,x64_avx512dq,
                    sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx,
                    avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
@@ -831,8 +831,6 @@
 (define_attr "enabled" ""
   (cond [(eq_attr "isa" "x64") (symbol_ref "TARGET_64BIT")
         (eq_attr "isa" "nox64") (symbol_ref "!TARGET_64BIT")
-        (eq_attr "isa" "x64_bmi")
-          (symbol_ref "TARGET_64BIT && TARGET_BMI")
         (eq_attr "isa" "x64_sse2")
           (symbol_ref "TARGET_64BIT && TARGET_SSE2")
         (eq_attr "isa" "x64_sse4")

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 948ba479c32d497f22494693a4baab20cca44854..baeed04d8c94fb8b350830f644b2765901ba2ce9 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -2055,40 +2055,34 @@
   "operands[2] = force_reg (<MODE>mode, CONSTM1_RTX (<MODE>mode));")
 
 (define_insn "mmx_andnot<mode>3"
-  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,r,x,x,v")
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
        (and:MMXMODEI
-         (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand"
-           "0,r,0,x,v"))
-         (match_operand:MMXMODEI 2 "register_mmxmem_operand"
-           "ym,r,x,x,v")))]
+         (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0,0,x,v"))
+         (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
   "TARGET_MMX || TARGET_MMX_WITH_SSE"
   "@
    pandn\t{%2, %0|%0, %2}
-   andn\t{%2, %1, %0|%0, %1, %2}
    pandn\t{%2, %0|%0, %2}
    vpandn\t{%2, %1, %0|%0, %1, %2}
    vpandnd\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "isa" "*,x64_bmi,sse2_noavx,avx,avx512vl")
-   (set_attr "mmx_isa" "native,*,*,*,*")
-   (set_attr "type" "mmxadd,bitmanip,sselog,sselog,sselog")
-   (set_attr "btver2_decode" "*,direct,*,*,*")
-   (set_attr "mode" "DI,DI,TI,TI,TI")])
+  [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
+   (set_attr "mmx_isa" "native,*,*,*")
+   (set_attr "type" "mmxadd,sselog,sselog,sselog")
+   (set_attr "mode" "DI,TI,TI,TI")])
 
 (define_insn "*andnot<mode>3"
-  [(set (match_operand:VI_32 0 "register_operand" "=r,x,x,v")
+  [(set (match_operand:VI_32 0 "register_operand" "=x,x,v")
        (and:VI_32
-         (not:VI_32 (match_operand:VI_32 1 "register_operand" "r,0,x,v"))
-         (match_operand:VI_32 2 "register_operand" "r,x,x,v")))]
+         (not:VI_32 (match_operand:VI_32 1 "register_operand" "0,x,v"))
+         (match_operand:VI_32 2 "register_operand" "x,x,v")))]
   "TARGET_SSE2"
   "@
-   andn\t{%2, %1, %0|%0, %1, %2}
    pandn\t{%2, %0|%0, %2}
    vpandn\t{%2, %1, %0|%0, %1, %2}
    vpandnd\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "isa" "bmi,noavx,avx,avx512vl")
-   (set_attr "type" "bitmanip,sselog,sselog,sselog")
-   (set_attr "btver2_decode" "direct,*,*,*")
-   (set_attr "mode" "SI,TI,TI,TI")])
+  [(set_attr "isa" "noavx,avx,avx512vl")
+   (set_attr "type" "sselog")
+   (set_attr "mode" "TI")])
 
 (define_expand "mmx_<code><mode>3"
   [(set (match_operand:MMXMODEI 0 "register_operand")
@@ -2107,22 +2101,21 @@
   "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
 
 (define_insn "*mmx_<code><mode>3"
-  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,r,x,x,v")
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
         (any_logic:MMXMODEI
-         (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,0,x,v")
-         (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,r,x,x,v")))]
+         (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,x,v")
+         (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
   "(TARGET_MMX || TARGET_MMX_WITH_SSE)
    && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
   "@
    p<logic>\t{%2, %0|%0, %2}
-   <logic>\t{%2, %0|%0, %2}
    p<logic>\t{%2, %0|%0, %2}
    vp<logic>\t{%2, %1, %0|%0, %1, %2}
    vp<logic>d\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "isa" "*,x64,sse2_noavx,avx,avx512vl")
-   (set_attr "mmx_isa" "native,*,*,*,*")
-   (set_attr "type" "mmxadd,alu,sselog,sselog,sselog")
-   (set_attr "mode" "DI,DI,TI,TI,TI")])
+  [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
+   (set_attr "mmx_isa" "native,*,*,*")
+   (set_attr "type" "mmxadd,sselog,sselog,sselog")
+   (set_attr "mode" "DI,TI,TI,TI")])
 
 (define_expand "<code><mode>3"
   [(set (match_operand:VI_32 0 "register_operand")
@@ -2133,20 +2126,19 @@
   "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
 
 (define_insn "*<code><mode>3"
-  [(set (match_operand:VI_32 0 "register_operand" "=r,x,x,v")
+  [(set (match_operand:VI_32 0 "register_operand" "=x,x,v")
         (any_logic:VI_32
-         (match_operand:VI_32 1 "register_operand" "%0,0,x,v")
-         (match_operand:VI_32 2 "register_operand" "r,x,x,v")))]
+         (match_operand:VI_32 1 "register_operand" "%0,x,v")
+         (match_operand:VI_32 2 "register_operand" "x,x,v")))]
   "TARGET_SSE2
    && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
   "@
-   <logic>\t{%2, %0|%0, %2}
    p<logic>\t{%2, %0|%0, %2}
    vp<logic>\t{%2, %1, %0|%0, %1, %2}
    vp<logic>d\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "isa" "*,noavx,avx,avx512vl")
-   (set_attr "type" "alu,sselog,sselog,sselog")
-   (set_attr "mode" "SI,TI,TI,TI")])
+  [(set_attr "isa" "noavx,avx,avx512vl")
+   (set_attr "type" "sselog")
+   (set_attr "mode" "TI")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;

diff --git a/gcc/testsuite/gcc.target/i386/pr100701.c b/gcc/testsuite/gcc.target/i386/pr100701.c
new file mode 100644 (file)
index 0000000..3132d66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr100701.c
@@ -0,0 +1,28 @@
+/* PR target/100701 */
+/* { dg-do run { target { ! ia32 } } } */
+/* { dg-options "-O0 -fschedule-insns2 -msse2" } */
+
+typedef unsigned char __attribute__((__vector_size__ (8))) V;
+typedef unsigned int __attribute__((__vector_size__ (8))) U;
+
+U u;
+unsigned x;
+unsigned char y;
+
+V
+foo (V a, __int128 i)
+{
+  V b = a;
+  a &= y;
+  if (i == 0)
+    __builtin_abort ();
+  U c = (x != y / i) <= u;
+  return (V) c + a + b;
+}
+
+int
+main (void)
+{
+  (void)foo ((V) { }, 4);
+  return 0;
+}