sim: riscv: Make stack 16-byte aligned

Various gcc test cases fail due to the stack
alignment of 16 bytes is expected by gcc,
causing issues mostly with vararg functions,
e.g.

FAIL: gcc.c-torture/execute/nest-align-1.c   -O0  execution test
FAIL: gcc.c-torture/execute/nest-stdar-1.c   -O0  execution test
FAIL: gcc.c-torture/execute/va-arg-12.c   -O0  execution test
FAIL: gcc.c-torture/execute/va-arg-15.c   -O0  execution test
FAIL: gcc.c-torture/execute/va-arg-16.c   -O0  execution test
FAIL: gcc.c-torture/execute/va-arg-17.c   -O0  execution test
FAIL: gcc.c-torture/execute/va-arg-20.c   -O0  execution test
FAIL: gcc.c-torture/execute/va-arg-26.c   -O0  execution test
...

Approved-By: Andrew Burgess <aburgess@redhat.com>

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index ddc7e1d3e98b472b337942fe9288478660447412..1ccae450ad4826255a1cdc6bd9835a26fd65b86e 100644 (file)
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1575,6 +1575,8 @@ initialize_env (SIM_DESC sd, const char * const *argv, const char * const *env)
   sp = sp_flat - ((argc + 1 + envc + 1) * sizeof (address_word));
   /* Then the argc.  */
   sp -= sizeof (unsigned_word);
+  /* Align to 16 bytes.  */
+  sp = align_down (sp, 16);
 
   /* Set up the regs the libgloss crt0 expects.  */
   riscv_cpu->a0 = argc;