dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers

Add device tree bindings for syscon clock and reset controllers (IMGSYS,
MFGCFG, VDECSYS and VENCSYS).

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241106111402.200940-2-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml
index 10483e26878fb41308a4e4f0f72e0ae2a0fa940f..a86a64893c675ac134af609b3a49242565db6ad8 100644 (file)
--- a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml
@@ -28,6 +28,10 @@ properties:
               - mediatek,mt2712-mfgcfg
               - mediatek,mt2712-vdecsys
               - mediatek,mt2712-vencsys
+              - mediatek,mt6735-imgsys
+              - mediatek,mt6735-mfgcfg
+              - mediatek,mt6735-vdecsys
+              - mediatek,mt6735-vencsys
               - mediatek,mt6765-camsys
               - mediatek,mt6765-imgsys
               - mediatek,mt6765-mipi0a

diff --git a/MAINTAINERS b/MAINTAINERS
index 1c6063dc46ae2eedd86216992c8f1865e0b840bd..c6d4f0c48cda5e8c951fb65a50a65188b6782981 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14538,11 +14538,17 @@ F:    drivers/clk/mediatek/clk-mt6735-infracfg.c
 F:     drivers/clk/mediatek/clk-mt6735-pericfg.c
 F:     drivers/clk/mediatek/clk-mt6735-topckgen.c
 F:     include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
+F:     include/dt-bindings/clock/mediatek,mt6735-imgsys.h
 F:     include/dt-bindings/clock/mediatek,mt6735-infracfg.h
+F:     include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h
 F:     include/dt-bindings/clock/mediatek,mt6735-pericfg.h
 F:     include/dt-bindings/clock/mediatek,mt6735-topckgen.h
+F:     include/dt-bindings/clock/mediatek,mt6735-vdecsys.h
+F:     include/dt-bindings/clock/mediatek,mt6735-vencsys.h
 F:     include/dt-bindings/reset/mediatek,mt6735-infracfg.h
+F:     include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h
 F:     include/dt-bindings/reset/mediatek,mt6735-pericfg.h
+F:     include/dt-bindings/reset/mediatek,mt6735-vdecsys.h
 
 MEDIATEK MT76 WIRELESS LAN DRIVER
 M:     Felix Fietkau <nbd@nbd.name>

diff --git a/include/dt-bindings/clock/mediatek,mt6735-imgsys.h b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h
new file mode 100644 (file)
index 0000000..f250c26
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_IMGSYS_H
+#define _DT_BINDINGS_CLK_MT6735_IMGSYS_H
+
+#define CLK_IMG_SMI_LARB2              0
+#define CLK_IMG_CAM_SMI                        1
+#define CLK_IMG_CAM_CAM                        2
+#define CLK_IMG_SEN_TG                 3
+#define CLK_IMG_SEN_CAM                        4
+#define CLK_IMG_CAM_SV                 5
+#define CLK_IMG_SUFOD                  6
+#define CLK_IMG_FD                     7
+
+#endif /* _DT_BINDINGS_CLK_MT6735_IMGSYS_H */

diff --git a/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h
new file mode 100644 (file)
index 0000000..d2d99a4
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_MFGCFG_H
+#define _DT_BINDINGS_CLK_MT6735_MFGCFG_H
+
+#define CLK_MFG_BG3D                   0
+
+#endif /* _DT_BINDINGS_CLK_MT6735_MFGCFG_H */

diff --git a/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h
new file mode 100644 (file)
index 0000000..f94cec1
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_VDECSYS_H
+#define _DT_BINDINGS_CLK_MT6735_VDECSYS_H
+
+#define CLK_VDEC_VDEC                  0
+#define CLK_VDEC_SMI_LARB1             1
+
+#endif /* _DT_BINDINGS_CLK_MT6735_VDECSYS_H */

diff --git a/include/dt-bindings/clock/mediatek,mt6735-vencsys.h b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h
new file mode 100644 (file)
index 0000000..e5a9cb4
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_VENCSYS_H
+#define _DT_BINDINGS_CLK_MT6735_VENCSYS_H
+
+#define CLK_VENC_SMI_LARB3                     0
+#define CLK_VENC_VENC                  1
+#define CLK_VENC_JPGENC                        2
+#define CLK_VENC_JPGDEC                        3
+
+#endif /* _DT_BINDINGS_CLK_MT6735_VENCSYS_H */

diff --git a/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h
new file mode 100644 (file)
index 0000000..c489242
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_MFGCFG_H
+#define _DT_BINDINGS_RESET_MT6735_MFGCFG_H
+
+#define MT6735_MFG_RST0_AXI            0
+#define MT6735_MFG_RST0_G3D            1
+
+#endif /* _DT_BINDINGS_RESET_MT6735_MFGCFG_H */

diff --git a/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h
new file mode 100644 (file)
index 0000000..b6ae5d2
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_VDECSYS_H
+#define _DT_BINDINGS_RESET_MT6735_VDECSYS_H
+
+#define MT6735_VDEC_RST0_VDEC                  0
+#define MT6735_VDEC_RST1_SMI_LARB1             1
+
+#endif /* _DT_BINDINGS_RESET_MT6735_VDECSYS_H */