gas: sparc: Fix faligndatai assembly and disassembly

The first operand is a general register, not an fp register;
the third operand is encoded into RS2, not RS3;
the second operand must match the destination operand.

diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index aca60e6c4f5c9e9af4c884aa2751494024fe36e4..e37189e7c5ed13de6b3b299d1d61d1ab74983bcd 100644 (file)
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -2593,13 +2593,6 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
                    break;
                  }     /* if not an 'f' register.  */
 
-               if (*args == '}' && mask != RS2 (opcode))
-                 {
-                   error_message
-                     = _(": Instruction requires frs2 and frsd must be the same register");
-                   goto error;
-                 }
-
                switch (*args)
                  {
                  case 'v':
@@ -2628,10 +2621,18 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
                  case 'g':
                  case 'H':
                  case 'J':
-                 case '}':
                   case '^':
                    opcode |= RD (mask);
                    continue;
+
+                 case '}':
+                   if (RD (mask) != (opcode & RD (0x1f)))
+                     {
+                       error_message = _(": Instruction requires frs2 and "
+                                         "frsd must be the same register");
+                       goto error;
+                     }
+                   continue;
                  }             /* Pack it in.  */
 
                know (0);

diff --git a/gas/testsuite/gas/sparc/sparc5vis4.d b/gas/testsuite/gas/sparc/sparc5vis4.d
index bf5c90bbcf343e9b7176f95c6131a8212eef76e1..7820c2a5672b0061cc17919b83c2546a5d7cc274 100644 (file)
--- a/gas/testsuite/gas/sparc/sparc5vis4.d
+++ b/gas/testsuite/gas/sparc/sparc5vis4.d
@@ -35,4 +35,4 @@ Disassembly of section .text:
   64:  95 b1 aa c8     fpsubs8  %f6, %f8, %f10
   68:  9d b2 aa ec     fpsubus8  %f10, %f12, %f14
   6c:  a5 b3 aa 70     fpsubus16  %f14, %f16, %f18
-  70:  bf b0 09 3f     faligndata  %f0, %f62, %f4, %f62
+  70:  bf b0 09 24     faligndata  %g0, %f62, %f4, %f62

diff --git a/gas/testsuite/gas/sparc/sparc5vis4.s b/gas/testsuite/gas/sparc/sparc5vis4.s
index 0a0155f3376ab00fde91c6bf91b8e81ee53d38e3..58ca2b5f3688ffa54bfc322ddab1336ffdd69d9c 100644 (file)
--- a/gas/testsuite/gas/sparc/sparc5vis4.s
+++ b/gas/testsuite/gas/sparc/sparc5vis4.s
@@ -28,4 +28,4 @@
        fpsubs8 %f6, %f8, %f10
        fpsubus8 %f10, %f12, %f14
        fpsubus16 %f14, %f16, %f18
-       faligndata %f0, %f62, %f4, %f62
+       faligndata %g0, %f62, %f4, %f62

diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index fb7ebe38d468a7169a7acfe57546a44db3079b25..19f7f62f1a324c6f29db98e02ff8b098fba98709 100644 (file)
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -2016,7 +2016,7 @@ SLCBCC("cbnefr", 15),
 { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, 0, v9a },
 { "alignaddrl",        F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, 0, v9a },
 { "faligndata",        F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, 0, v9a }, /* faligndatag */
-{ "faligndata", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5, v9m }, /* faligndatai  */
+{ "faligndata", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "1,H,B,}", 0, 0, HWCAP2_SPARC5, v9m }, /* faligndatai  */
 
 { "fzerod",    F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, 0, v9a },
 { "fzero",     F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS, HWCAP_VIS, 0, v9a },