Merge branch 'kvm-arm64/el2-reg-visibility' into kvmarm/next

* kvm-arm64/el2-reg-visibility:
  : Fixes to EL2 register visibility, courtesy of Marc Zyngier
  :
  :  - Expose EL2 VGICv3 registers via the VGIC attributes accessor, not the
  :    KVM_{GET,SET}_ONE_REG ioctls
  :
  :  - Condition visibility of FGT registers on the presence of FEAT_FGT in
  :    the VM
  KVM: arm64: selftest: vgic-v3: Add basic GICv3 sysreg userspace access test
  KVM: arm64: Enforce the sorting of the GICv3 system register table
  KVM: arm64: Clarify the check for reset callback in check_sysreg_table()
  KVM: arm64: vgic-v3: Fix ordering of ICH_HCR_EL2
  KVM: arm64: Document registers exposed via KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
  KVM: arm64: selftests: get-reg-list: Add base EL2 registers
  KVM: arm64: selftests: get-reg-list: Simplify feature dependency
  KVM: arm64: Advertise FGT2 registers to userspace
  KVM: arm64: Condition FGT registers on feature availability
  KVM: arm64: Expose GICv3 EL2 registers via KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
  KVM: arm64: Let GICv3 save/restore honor visibility attribute
  KVM: arm64: Define helper for ICH_VTR_EL2
  KVM: arm64: Define constant value for ICC_SRE_EL2
  KVM: arm64: Don't advertise ICH_*_EL2 registers through GET_ONE_REG
  KVM: arm64: Make RVBAR_EL2 accesses UNDEF

Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --cc arch/arm64/kvm/sys_regs.c
index 93a6f87748ef0f8c0a32bc60bccffa303fc7c8e3,61bfe90efa20c4ceaf632eae4e5a0c7a0b73309a..ad25484772574086245fc5cb4bcd8c690c19ae8e
--- 1/arch/arm64/kvm/sys_regs.c
--- 2/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@@ -3417,18 -3399,17 +3446,18 @@@ static const struct sys_reg_desc sys_re
        { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access },
  
        EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
-       EL2_REG(RVBAR_EL2, access_rw, reset_val, 0),
+       { SYS_DESC(SYS_RVBAR_EL2), undef_access },
        { SYS_DESC(SYS_RMR_EL2), undef_access },
 +      EL2_REG_VNCR(VDISR_EL2, reset_unknown, 0),
  
-       EL2_REG_VNCR(ICH_AP0R0_EL2, reset_val, 0),
-       EL2_REG_VNCR(ICH_AP0R1_EL2, reset_val, 0),
-       EL2_REG_VNCR(ICH_AP0R2_EL2, reset_val, 0),
-       EL2_REG_VNCR(ICH_AP0R3_EL2, reset_val, 0),
-       EL2_REG_VNCR(ICH_AP1R0_EL2, reset_val, 0),
-       EL2_REG_VNCR(ICH_AP1R1_EL2, reset_val, 0),
-       EL2_REG_VNCR(ICH_AP1R2_EL2, reset_val, 0),
-       EL2_REG_VNCR(ICH_AP1R3_EL2, reset_val, 0),
+       EL2_REG_VNCR_GICv3(ICH_AP0R0_EL2),
+       EL2_REG_VNCR_GICv3(ICH_AP0R1_EL2),
+       EL2_REG_VNCR_GICv3(ICH_AP0R2_EL2),
+       EL2_REG_VNCR_GICv3(ICH_AP0R3_EL2),
+       EL2_REG_VNCR_GICv3(ICH_AP1R0_EL2),
+       EL2_REG_VNCR_GICv3(ICH_AP1R1_EL2),
+       EL2_REG_VNCR_GICv3(ICH_AP1R2_EL2),
+       EL2_REG_VNCR_GICv3(ICH_AP1R3_EL2),
  
        { SYS_DESC(SYS_ICC_SRE_EL2), access_gic_sre },
  

diff --cc arch/arm64/kvm/vgic/vgic.h
Simple merge

diff --cc tools/testing/selftests/kvm/arm64/get-reg-list.c
index 684c52b1b8817303bf6573dfc211325f94fcbaa8,996d78ee3548791485dcf31934220d0d8c9b7905..f4f85d12d42e8fcc87b2ab4d288c4e4f0ce81208
--- 1/tools/testing/selftests/kvm/arm64/get-reg-list.c
--- 2/tools/testing/selftests/kvm/arm64/get-reg-list.c
+++ b/tools/testing/selftests/kvm/arm64/get-reg-list.c
@@@ -22,43 -28,40 +28,41 @@@ struct feature_id_reg 
        __u64 feat_min;
  };
  
- static struct feature_id_reg feat_id_regs[] = {
-       {
-               ARM64_SYS_REG(3, 0, 2, 0, 3),   /* TCR2_EL1 */
-               ARM64_SYS_REG(3, 0, 0, 7, 3),   /* ID_AA64MMFR3_EL1 */
-               0,
-               1
-       },
-       {
-               ARM64_SYS_REG(3, 0, 10, 2, 2),  /* PIRE0_EL1 */
-               ARM64_SYS_REG(3, 0, 0, 7, 3),   /* ID_AA64MMFR3_EL1 */
-               8,
-               1
-       },
-       {
-               ARM64_SYS_REG(3, 0, 10, 2, 3),  /* PIR_EL1 */
-               ARM64_SYS_REG(3, 0, 0, 7, 3),   /* ID_AA64MMFR3_EL1 */
-               8,
-               1
-       },
-       {
-               ARM64_SYS_REG(3, 0, 10, 2, 4),  /* POR_EL1 */
-               ARM64_SYS_REG(3, 0, 0, 7, 3),   /* ID_AA64MMFR3_EL1 */
-               16,
-               1
-       },
-       {
-               ARM64_SYS_REG(3, 3, 10, 2, 4),  /* POR_EL0 */
-               ARM64_SYS_REG(3, 0, 0, 7, 3),   /* ID_AA64MMFR3_EL1 */
-               16,
-               1
-       },
-       {
-               KVM_ARM64_SYS_REG(SYS_SCTLR2_EL1),
-               KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR3_EL1),
-               ID_AA64MMFR3_EL1_SCTLRX_SHIFT,
-               ID_AA64MMFR3_EL1_SCTLRX_IMP
+ #define FEAT(id, f, v)                                        \
+       .id_reg         = SYS_REG(id),                  \
+       .feat_shift     = id ## _ ## f ## _SHIFT,       \
+       .feat_min       = id ## _ ## f ## _ ## v
+ 
+ #define REG_FEAT(r, id, f, v)                 \
+       {                                       \
+               .reg = SYS_REG(r),              \
+               FEAT(id, f, v)                  \
        }
+ 
+ static struct feature_id_reg feat_id_regs[] = {
+       REG_FEAT(TCR2_EL1,      ID_AA64MMFR3_EL1, TCRX, IMP),
+       REG_FEAT(TCR2_EL2,      ID_AA64MMFR3_EL1, TCRX, IMP),
+       REG_FEAT(PIRE0_EL1,     ID_AA64MMFR3_EL1, S1PIE, IMP),
+       REG_FEAT(PIRE0_EL2,     ID_AA64MMFR3_EL1, S1PIE, IMP),
+       REG_FEAT(PIR_EL1,       ID_AA64MMFR3_EL1, S1PIE, IMP),
+       REG_FEAT(PIR_EL2,       ID_AA64MMFR3_EL1, S1PIE, IMP),
+       REG_FEAT(POR_EL1,       ID_AA64MMFR3_EL1, S1POE, IMP),
+       REG_FEAT(POR_EL0,       ID_AA64MMFR3_EL1, S1POE, IMP),
+       REG_FEAT(POR_EL2,       ID_AA64MMFR3_EL1, S1POE, IMP),
+       REG_FEAT(HCRX_EL2,      ID_AA64MMFR1_EL1, HCX, IMP),
+       REG_FEAT(HFGRTR_EL2,    ID_AA64MMFR0_EL1, FGT, IMP),
+       REG_FEAT(HFGWTR_EL2,    ID_AA64MMFR0_EL1, FGT, IMP),
+       REG_FEAT(HFGITR_EL2,    ID_AA64MMFR0_EL1, FGT, IMP),
+       REG_FEAT(HDFGRTR_EL2,   ID_AA64MMFR0_EL1, FGT, IMP),
+       REG_FEAT(HDFGWTR_EL2,   ID_AA64MMFR0_EL1, FGT, IMP),
+       REG_FEAT(HAFGRTR_EL2,   ID_AA64MMFR0_EL1, FGT, IMP),
+       REG_FEAT(HFGRTR2_EL2,   ID_AA64MMFR0_EL1, FGT, FGT2),
+       REG_FEAT(HFGWTR2_EL2,   ID_AA64MMFR0_EL1, FGT, FGT2),
+       REG_FEAT(HFGITR2_EL2,   ID_AA64MMFR0_EL1, FGT, FGT2),
+       REG_FEAT(HDFGRTR2_EL2,  ID_AA64MMFR0_EL1, FGT, FGT2),
+       REG_FEAT(HDFGWTR2_EL2,  ID_AA64MMFR0_EL1, FGT, FGT2),
+       REG_FEAT(ZCR_EL2,       ID_AA64PFR0_EL1, SVE, IMP),
++      REG_FEAT(SCTLR2_EL1,    ID_AA64MMFR3_EL1, SCTLRX, IMP),
  };
  
  bool filter_reg(__u64 reg)