]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
firmware: qcom_scm: Add set remote state API
authorAndy Gross <andy.gross@linaro.org>
Tue, 17 Jan 2017 05:24:15 +0000 (23:24 -0600)
committerAndy Gross <andy.gross@linaro.org>
Tue, 17 Jan 2017 05:45:04 +0000 (23:45 -0600)
This patch adds a set remote state SCM API.  This will be used by the
Venus and GPU subsystems to set state on the remote processors.

This work was based on two patch sets by Jordan Crouse and Stanimir
Varbanov.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
drivers/firmware/qcom_scm-32.c
drivers/firmware/qcom_scm-64.c
drivers/firmware/qcom_scm.c
drivers/firmware/qcom_scm.h
include/linux/qcom_scm.h

index c6aeedbdcbb0095b8d08c9319d7dfc6650e9ba58..8ad226c60374cd9a2697268c4137212d63673f7f 100644 (file)
@@ -560,3 +560,21 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
 
        return ret ? : le32_to_cpu(out);
 }
+
+int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
+{
+       struct {
+               __le32 state;
+               __le32 id;
+       } req;
+       __le32 scm_ret = 0;
+       int ret;
+
+       req.state = cpu_to_le32(state);
+       req.id = cpu_to_le32(id);
+
+       ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE,
+                           &req, sizeof(req), &scm_ret, sizeof(scm_ret));
+
+       return ret ? : le32_to_cpu(scm_ret);
+}
index 4a0f5ead4fb57eeae9f4491f61d4c5c433999b3d..4b220abaf3633a05a5a5eb2ca7db0e6e013dcbda 100644 (file)
@@ -358,3 +358,19 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
 
        return ret ? : res.a1;
 }
+
+int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
+{
+       struct qcom_scm_desc desc = {0};
+       struct arm_smccc_res res;
+       int ret;
+
+       desc.args[0] = state;
+       desc.args[1] = id;
+       desc.arginfo = QCOM_SCM_ARGS(2);
+
+       ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE,
+                           &desc, &res);
+
+       return ret ? : res.a1;
+}
index 65d0d9d64ebbc723cdf625d605ec82609bf7c362..d987bcc7489d981ee4b9784a6293fa6fd6ce175a 100644 (file)
@@ -324,6 +324,12 @@ bool qcom_scm_is_available(void)
 }
 EXPORT_SYMBOL(qcom_scm_is_available);
 
+int qcom_scm_set_remote_state(u32 state, u32 id)
+{
+       return __qcom_scm_set_remote_state(__scm->dev, state, id);
+}
+EXPORT_SYMBOL(qcom_scm_set_remote_state);
+
 static int qcom_scm_probe(struct platform_device *pdev)
 {
        struct qcom_scm *scm;
index 3584b00fe7e6424f16f50c2b238aeb878646c10e..6a0f15469344e0b960747a3d06f4236467da942f 100644 (file)
@@ -15,6 +15,8 @@
 #define QCOM_SCM_SVC_BOOT              0x1
 #define QCOM_SCM_BOOT_ADDR             0x1
 #define QCOM_SCM_BOOT_ADDR_MC          0x11
+#define QCOM_SCM_SET_REMOTE_STATE      0xa
+extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
 
 #define QCOM_SCM_FLAG_HLOS             0x01
 #define QCOM_SCM_FLAG_COLDBOOT_MC      0x02
index 7e004fb57fc4ecc7e1842000bd0c6f3559e5c5ed..d32f6f1a5225f38de2ff8456a09b236028eb1de5 100644 (file)
@@ -39,6 +39,7 @@ extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
 extern int qcom_scm_pas_shutdown(u32 peripheral);
 extern void qcom_scm_cpu_power_down(u32 flags);
 extern u32 qcom_scm_get_version(void);
+extern int qcom_scm_set_remote_state(u32 state, u32 id);
 #else
 static inline
 int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
@@ -64,6 +65,7 @@ qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
 static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
 static inline void qcom_scm_cpu_power_down(u32 flags) {}
 static inline u32 qcom_scm_get_version(void) { return 0; }
+static inline u32
+qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
 #endif
-
 #endif