{
rtx reg1 = gen_reg_rtx (DImode);
rtx reg2 = gen_reg_rtx (DImode);
+ rtx rd = gen_reg_rtx (DImode);
operands[1] = gen_rtx_SIGN_EXTEND (word_mode, operands[1]);
operands[2] = gen_rtx_SIGN_EXTEND (word_mode, operands[2]);
emit_insn (gen_rtx_SET (reg1, operands[1]));
emit_insn (gen_rtx_SET (reg2, operands[2]));
- emit_insn (gen_<optab>di3_fake (operands[0], reg1, reg2));
+ emit_insn (gen_<optab>di3_fake (rd, reg1, reg2));
+ emit_insn (gen_rtx_SET (operands[0],
+ simplify_gen_subreg (SImode, rd, DImode, 0)));
DONE;
}
})
(const_string "no")))])
(define_insn "<optab>di3_fake"
- [(set (match_operand:SI 0 "register_operand" "=r,&r,&r")
- (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0")
- (match_operand:DI 2 "register_operand" "r,r,r")))]
+ [(set (match_operand:DI 0 "register_operand" "=r,&r,&r")
+ (sign_extend:DI
+ (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0")
+ (match_operand:DI 2 "register_operand" "r,r,r"))))]
""
{
return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);