drm/i915: move rawclk from runtime to display runtime info

It's mostly about display, so move it under display. This should also
fix rawclk freq initialization in the xe driver.

v2: Change the init location

Link: https://lore.kernel.org/r/20240819133138.147511-2-maarten.lankhorst@linux.intel.com
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/39330d09c48509e013f01fd0247a9b7c291173e2.1724144570.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 18933b003cbef79baf277904b2812cdd5b163fbd..9e05745d797d1945eceb5970f1993d9e760edeb0 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1011,7 +1011,7 @@ static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 {
        struct drm_i915_private *i915 = to_i915(connector->base.dev);
 
-       return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
+       return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
                                 pwm_freq_hz);
 }
 
@@ -1073,7 +1073,7 @@ static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 {
        struct drm_i915_private *i915 = to_i915(connector->base.dev);
 
-       return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
+       return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
                                 pwm_freq_hz * 128);
 }
 
@@ -1091,7 +1091,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
        int clock;
 
        if (IS_PINEVIEW(i915))
-               clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+               clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
        else
                clock = KHz(i915->display.cdclk.hw.cdclk);
 
@@ -1109,7 +1109,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
        int clock;
 
        if (IS_G4X(i915))
-               clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+               clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
        else
                clock = KHz(i915->display.cdclk.hw.cdclk);
 
@@ -1133,7 +1133,7 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
                        clock = MHz(25);
                mul = 16;
        } else {
-               clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+               clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
                mul = 128;
        }
 

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index a31f89df2c0ab8afc81376c47b02d77e22d18786..b28d55fa0c3a314c2a1b000a4e6f88cd59f8df02 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1474,6 +1474,9 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9
                }
        }
 
+       display_runtime->rawclk_freq = intel_read_rawclk(i915);
+       drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq);
+
        return;
 
 display_fused_off:
@@ -1516,6 +1519,8 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf
        drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
        drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
        drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
+
+       drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
 }
 
 /*

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 13453ea4daea09c2d77816a79c2cf7ec0b3b410a..ad60c676c84d144948f3eb798fec14344cc86ae3 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -204,6 +204,8 @@ struct intel_display_runtime_info {
                u16 step;
        } ip;
 
+       u32 rawclk_freq;
+
        u8 pipe_mask;
        u8 cpu_transcoder_mask;
        u16 port_mask;

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 919f712fef131cecd0988b3791daaa9bbf71775c..adf5d1fbccb562c0a7bdb4c7fc148a43e0c18746 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1176,9 +1176,9 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
                       MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
        intel_de_write(dev_priv, CBR1_VLV, 0);
 
-       drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
+       drm_WARN_ON(&dev_priv->drm, DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
        intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
-                      DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
+                      DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq,
                                         1000));
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index b8a53bb174dab9c18fba47344b825c98ac211287..cbc817bb0cc3ecccaf10a01acada044c8902c022 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -83,7 +83,7 @@ static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
         * The clock divider is based off the hrawclk, and would like to run at
         * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
         */
-       return DIV_ROUND_CLOSEST(RUNTIME_INFO(i915)->rawclk_freq, 2000);
+       return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq, 2000);
 }
 
 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
@@ -103,7 +103,7 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
        if (dig_port->aux_ch == AUX_CH_A)
                freq = i915->display.cdclk.hw.cdclk;
        else
-               freq = RUNTIME_INFO(i915)->rawclk_freq;
+               freq = DISPLAY_RUNTIME_INFO(i915)->rawclk_freq;
        return DIV_ROUND_CLOSEST(freq, 2000);
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 0918eb218fc84835213b5aa789107e503ebe37da..68141af4da540f11fd5e961bf61225c6c8834fb8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1483,7 +1483,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        u32 pp_on, pp_off, port_sel = 0;
-       int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
+       int div = DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
        struct pps_registers regs;
        enum port port = dp_to_dig_port(intel_dp)->base.port;
        const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d26de37719a72b3887fd1bb2360a991d20062264..91acbf99574c32106f7e6c97a5f46f76bcd06d17 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -124,7 +124,6 @@ void intel_device_info_print(const struct intel_device_info *info,
 #undef PRINT_FLAG
 
        drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
-       drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
 }
 
 #define ID(id) (id)
@@ -370,10 +369,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                         "Disabling ppGTT for VT-d support\n");
                runtime->ppgtt_type = INTEL_PPGTT_NONE;
        }
-
-       runtime->rawclk_freq = intel_read_rawclk(dev_priv);
-       drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
-
 }
 
 /*

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d1a2abc7e513930010d67d2c8526e4d0507eca58..fb8a08623eb01720ee7dee141def2aba96ea8049 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -204,8 +204,6 @@ struct intel_runtime_info {
 
        u16 device_id;
 
-       u32 rawclk_freq;
-
        struct intel_step_info step;
 
        unsigned int page_sizes; /* page sizes supported by the HW */