6.0-stable patches

added patches:
	drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch

diff --git a/queue-6.0/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch b/queue-6.0/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch
new file mode 100644 (file)
index 0000000..e376966
--- /dev/null
+++ b/queue-6.0/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch
@@ -0,0 +1,39 @@
+From 04aa64375f48a5d430b5550d9271f8428883e550 Mon Sep 17 00:00:00 2001
+From: Andrzej Hajda <andrzej.hajda@intel.com>
+Date: Mon, 14 Nov 2022 11:38:24 +0100
+Subject: drm/i915: fix TLB invalidation for Gen12 video and compute engines
+
+From: Andrzej Hajda <andrzej.hajda@intel.com>
+
+commit 04aa64375f48a5d430b5550d9271f8428883e550 upstream.
+
+In case of Gen12 video and compute engines, TLB_INV registers are masked -
+to modify one bit, corresponding bit in upper half of the register must
+be enabled, otherwise nothing happens.
+
+CVE: CVE-2022-4139
+Suggested-by: Chris Wilson <chris.p.wilson@intel.com>
+Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
+Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
+Cc: stable@vger.kernel.org
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/gt/intel_gt.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/gpu/drm/i915/gt/intel_gt.c
++++ b/drivers/gpu/drm/i915/gt/intel_gt.c
+@@ -961,6 +961,11 @@ static void mmio_invalidate_full(struct
+               if (!i915_mmio_reg_offset(rb.reg))
+                       continue;
+ 
++              if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS ||
++                  engine->class == VIDEO_ENHANCEMENT_CLASS ||
++                  engine->class == COMPUTE_CLASS))
++                      rb.bit = _MASKED_BIT_ENABLE(rb.bit);
++
+               intel_uncore_write_fw(uncore, rb.reg, rb.bit);
+               awake |= engine->mask;
+       }

diff --git a/queue-6.0/series b/queue-6.0/series
index 72b23db7aa343cf69bf9afaf758c6d9e3d4af46b..16bf6980f024dd9bcbf4ab89182a29346a9e5be2 100644 (file)
--- a/queue-6.0/series
+++ b/queue-6.0/series
@@ -286,3 +286,4 @@ drm-amd-amdgpu-reserve-vm-invalidation-engine-for-firmware.patch
 drm-amd-display-update-soc-bounding-box-for-dcn32-dcn321.patch
 drm-amdgpu-always-register-an-mmu-notifier-for-userptr.patch
 drm-amdgpu-partially-revert-drm-amdgpu-update-drm_display_info-correctly-when-the-edid-is-read.patch
+drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch