]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
PCI: al: Check IORESOURCE_BUS existence during probe
authorAleksandr Mishin <amishin@t-argos.ru>
Fri, 3 May 2024 12:57:05 +0000 (15:57 +0300)
committerBjorn Helgaas <bhelgaas@google.com>
Tue, 28 May 2024 16:14:24 +0000 (11:14 -0500)
If IORESOURCE_BUS is not provided in Device Tree it will be fabricated in
of_pci_parse_bus_range(), so NULL pointer dereference should not happen
here.

But that's hard to verify, so check for NULL anyway.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Link: https://lore.kernel.org/linux-pci/20240503125705.46055-1-amishin@t-argos.ru
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Aleksandr Mishin <amishin@t-argos.ru>
Signed-off-by: Krzysztof WilczyƄski <kwilczynski@kernel.org>
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/controller/dwc/pcie-al.c

index 6dfdda59f32836a21b10b4c6f88d3746d1e1462a..643115f74092d1c9319e9738db6e94b2752d30c4 100644 (file)
@@ -242,18 +242,24 @@ static struct pci_ops al_child_pci_ops = {
        .write = pci_generic_config_write,
 };
 
-static void al_pcie_config_prepare(struct al_pcie *pcie)
+static int al_pcie_config_prepare(struct al_pcie *pcie)
 {
        struct al_pcie_target_bus_cfg *target_bus_cfg;
        struct dw_pcie_rp *pp = &pcie->pci->pp;
        unsigned int ecam_bus_mask;
+       struct resource_entry *ft;
        u32 cfg_control_offset;
+       struct resource *bus;
        u8 subordinate_bus;
        u8 secondary_bus;
        u32 cfg_control;
        u32 reg;
-       struct resource *bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res;
 
+       ft = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS);
+       if (!ft)
+               return -ENODEV;
+
+       bus = ft->res;
        target_bus_cfg = &pcie->target_bus_cfg;
 
        ecam_bus_mask = (pcie->ecam_size >> PCIE_ECAM_BUS_SHIFT) - 1;
@@ -287,6 +293,8 @@ static void al_pcie_config_prepare(struct al_pcie *pcie)
               FIELD_PREP(CFG_CONTROL_SEC_BUS_MASK, secondary_bus);
 
        al_pcie_controller_writel(pcie, cfg_control_offset, reg);
+
+       return 0;
 }
 
 static int al_pcie_host_init(struct dw_pcie_rp *pp)
@@ -305,7 +313,9 @@ static int al_pcie_host_init(struct dw_pcie_rp *pp)
        if (rc)
                return rc;
 
-       al_pcie_config_prepare(pcie);
+       rc = al_pcie_config_prepare(pcie);
+       if (rc)
+               return rc;
 
        return 0;
 }