another .27 patch

diff --git a/queue-2.6.27/series b/queue-2.6.27/series
index 8da0913a3179d760f1522fead0e0f098fc07c2f5..ef169e9476f98103c2b908d64080de36b2f04e30 100644 (file)
--- a/queue-2.6.27/series
+++ b/queue-2.6.27/series
@@ -11,3 +11,4 @@ x86-fix-assembly-constraints-in-native_save_fl.patch
 parisc-ensure-broadcast-tlb-purge-runs-single-threaded.patch
 ieee1394-sbp2-add-support-for-disks-2-tb.patch
 firewire-sbp2-add-support-for-disks-2-tb.patch
+x86-enable-gart-iommu-only-after-setting-up-protection-methods.patch

diff --git a/queue-2.6.27/x86-enable-gart-iommu-only-after-setting-up-protection-methods.patch b/queue-2.6.27/x86-enable-gart-iommu-only-after-setting-up-protection-methods.patch
new file mode 100644 (file)
index 0000000..f0d1961
--- /dev/null
+++ b/queue-2.6.27/x86-enable-gart-iommu-only-after-setting-up-protection-methods.patch
@@ -0,0 +1,60 @@
+From fe2245c905631a3a353504fc04388ce3dfaf9d9e Mon Sep 17 00:00:00 2001
+From: Mark Langsdorf <mark.langsdorf@amd.com>
+Date: Sun, 5 Jul 2009 15:50:52 -0500
+Subject: x86: enable GART-IOMMU only after setting up protection methods
+
+From: Mark Langsdorf <mark.langsdorf@amd.com>
+
+commit fe2245c905631a3a353504fc04388ce3dfaf9d9e upstream.
+
+The current code to set up the GART as an IOMMU enables GART
+translations before it removes the aperture from the kernel memory
+map, sets the GART PTEs to UC, sets up the guard and scratch
+pages, or does a wbinvd().  This leaves the possibility of cache
+aliasing open and can cause system crashes.
+
+Re-order the code so as to enable the GART translations only
+after all safeguards are in place and the tlb has been flushed.
+
+AMD has tested this patch on both Istanbul systems and 1st
+generation Opteron systems with APG enabled and seen no adverse
+effects.  Istanbul systems with HT Assist enabled sometimes
+see MCE errors due to cache artifacts with the unmodified
+code.
+
+Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
+Cc: Joerg Roedel <joerg.roedel@amd.com>
+Cc: akpm@linux-foundation.org
+Cc: jbarnes@virtuousgeek.org
+Signed-off-by: Ingo Molnar <mingo@elte.hu>
+
+---
+ arch/x86/kernel/pci-gart_64.c |   10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/kernel/pci-gart_64.c
++++ b/arch/x86/kernel/pci-gart_64.c
+@@ -658,8 +658,6 @@ static __init int init_k8_gatt(struct ag
+       memset(gatt, 0, gatt_size);
+       agp_gatt_table = gatt;
+ 
+-      enable_gart_translations();
+-
+       error = sysdev_class_register(&gart_sysdev_class);
+       if (!error)
+               error = sysdev_register(&device_gart);
+@@ -828,6 +826,14 @@ void __init gart_iommu_init(void)
+       wbinvd();
+ 
+       /*
++       * Now all caches are flushed and we can safely enable
++       * GART hardware.  Doing it early leaves the possibility
++       * of stale cache entries that can lead to GART PTE
++       * errors.
++       */
++      enable_gart_translations();
++
++      /*
+        * Try to workaround a bug (thanks to BenH):
+        * Set unmapped entries to a scratch page instead of 0.
+        * Any prefetches that hit unmapped entries won't get an bus abort