arm64 cleanup, part 1

Mainly typos but also fix a potential assert in get_cache_info.

diff --git a/NEWS b/NEWS
index d10e75a091eba8c8f5eb302e72ad9dddbd9c8f98..cc47dd06561268ca72c261f6936020c49f5b901f 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -31,6 +31,7 @@ are not entered into bugzilla tend to get forgotten about or ignored.
         0x66 0xF 0x3A 0x2
 377966  arm64 unhandled instruction dc zva392146  aarch64: unhandled
         instruction 0xD5380001 (MRS rT, midr_el1)
+392146  aarch64: unhandled instruction 0xD5380001 (MRS rT, midr_el1)
 412377  SIGILL on cache flushes on arm64
 447989  Support Armv8.2 SHA-512 instructions
 486180  [Valgrind][MIPS] 'VexGuestArchState' has no member named

diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index 758b3970429afa52e0d1300952bb1396133be771..c3957bf58b269c1863d7246865f5ba6225bad3ca 100644 (file)
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -7569,7 +7569,7 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
       return True;
    }
    /* ---- Case for MPIDR_EL1 (RO) ----
-      Instead of returing a fake regiser, we use the same
+      Instead of returing a fake register, we use the same
       value as does the kernel emulation.
       0xD53800 101 Rt   MRS rT, mpidr_el1
    */
@@ -7580,7 +7580,7 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
       return True;
    }
    /* ---- Case for REVDIR_EL1 (RO) ----
-      Instead of emulating the regiser, we just return the same
+      Instead of emulating the register, we just return the same
       value as does the kernel emulation.
       0xD53800 110 Rt   MRS rT, revdir_el1
    */
@@ -7591,7 +7591,7 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
       return True;
    }
    /* ---- Case for ID_AA64PFR0_EL1 (RO) ----
-      Instead of returing a fake regiser, we use the same
+      Instead of returing a fake register, we use the same
       value as does the kernel emulation. We set deprecate half
       precission floating-point to normal floating-point support.
       We set all other values to zero.
@@ -7726,7 +7726,7 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
       return True;
    }
    /* ---- Case for ID_AA64MMFR0_EL1 (RO) ----
-      Instead of returing a fake regiser, we use the same
+      Instead of returing a fake register, we use the same
       value as does the kernel emulation.
       0xD53807 000 Rt   MRS rT, id_aa64mmfr0_el1
    */
@@ -7748,7 +7748,7 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
       return True;
    }
    /* ---- Case for ID_AA64MMFR1_EL1 (RO) ----
-      Instead of returing a fake regiser, we use the same
+      Instead of returing a fake register, we use the same
       value as does the kernel emulation. Set VHE and HAFDBS
       to not implemented.
       0xD53807 001 Rt   MRS rT, id_aa64mmfr1_el1
@@ -14110,7 +14110,6 @@ Bool dis_AdvSIMD_two_reg_misc(/*MB_OUT*/DisResult* dres, UInt insn)
          case 2: ch = 'm'; irrmE = mkU32(Irrm_NegINF); break;
          case 3: ch = 'p'; irrmE = mkU32(Irrm_PosINF); break;
          case 4: ch = 'z'; irrmE = mkU32(Irrm_ZERO); break;
-         // The following is a kludge.  Should be: Irrm_NEAREST_TIE_AWAY_0
          case 5: ch = 'a'; isBinop = False; op = isD ? Iop_RoundF64toIntA0 : Iop_RoundF32toIntA0; break;
          // I am unsure about the following, due to the "integral exact"
          // description in the manual.  What does it mean? (frintx, that is)

diff --git a/coregrind/m_cache.c b/coregrind/m_cache.c
index 2b32660c449b3d9fcf6ca035a409237e613154be..565aa4176771aecb1c55f00d71f8f1ced84bbee7 100644 (file)
--- a/coregrind/m_cache.c
+++ b/coregrind/m_cache.c
@@ -546,6 +546,7 @@ get_cache_info(VexArchInfo *vai)
 #if defined(VGA_arm64)
    unsigned long val;
    asm volatile("mrs %0, dczid_el0" : "=r" (val));
+   val &= 0xf;
    // The ARM manual says that 4 bits are used but 9 is the maximum
    vg_assert(val <= 9);
    vai->arm64_cache_block_size = val;