]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commitdiff
aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)
authorMatthieu Longo <matthieu.longo@arm.com>
Wed, 3 Jul 2024 17:37:45 +0000 (18:37 +0100)
committerMatthieu Longo <matthieu.longo@arm.com>
Fri, 5 Jul 2024 14:39:28 +0000 (15:39 +0100)
This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.

gas/testsuite/gas/aarch64/sysreg/sysreg.d
gas/testsuite/gas/aarch64/sysreg/sysreg.s
opcodes/aarch64-sys-regs.def

index 54ade34a87ea84b6f914c2b8a1d8275e7cdfeae1..4fa9f0d559d72ea18e53fa7320603e38f7f76ba8 100644 (file)
@@ -11,6 +11,11 @@ Disassembly of section \.text:
 .*:    d53b9c60        mrs     x0, pmovsclr_el0
 .*:    d51b9e60        msr     pmovsset_el0, x0
 .*:    d53b9e60        mrs     x0, pmovsset_el0
+.*:    d5380580        mrs     x0, id_aa64afr0_el1
+.*:    d53805a0        mrs     x0, id_aa64afr1_el1
+.*:    d5380500        mrs     x0, id_aa64dfr0_el1
+.*:    d5380520        mrs     x0, id_aa64dfr1_el1
+.*:    d5380540        mrs     x0, id_aa64dfr2_el1
 .*:    d5380140        mrs     x0, id_dfr0_el1
 .*:    d5380100        mrs     x0, id_pfr0_el1
 .*:    d5380120        mrs     x0, id_pfr1_el1
index 9c0fd4ae2fdbbbaf371ef1d6b5bcb19659904c83..cf0461412b599fa860faad9461df17ed90a8effb 100644 (file)
@@ -5,6 +5,11 @@
        rw_sys_reg sys_reg=pmovsclr_el0
        rw_sys_reg sys_reg=pmovsset_el0
 
+       rw_sys_reg sys_reg=id_aa64afr0_el1 w=0
+       rw_sys_reg sys_reg=id_aa64afr1_el1 w=0
+       rw_sys_reg sys_reg=id_aa64dfr0_el1 w=0
+       rw_sys_reg sys_reg=id_aa64dfr1_el1 w=0
+       rw_sys_reg sys_reg=id_aa64dfr2_el1 w=0
        rw_sys_reg sys_reg=id_dfr0_el1 w=0
        rw_sys_reg sys_reg=id_pfr0_el1 w=0
        rw_sys_reg sys_reg=id_pfr1_el1 w=0
index cd2f1ac8516ff1ef78b914fd4aec13a8e80aed96..6a554d9a12a47b91978668b66fb7eb3f9460f241 100644 (file)
   SYSREG ("id_aa64afr1_el1",   CPENC (3,0,0,5,5),      F_REG_READ,             AARCH64_NO_FEATURES)
   SYSREG ("id_aa64dfr0_el1",   CPENC (3,0,0,5,0),      F_REG_READ,             AARCH64_NO_FEATURES)
   SYSREG ("id_aa64dfr1_el1",   CPENC (3,0,0,5,1),      F_REG_READ,             AARCH64_NO_FEATURES)
+  SYSREG ("id_aa64dfr2_el1",   CPENC (3,0,0,5,2),      F_REG_READ,             AARCH64_NO_FEATURES)
   SYSREG ("id_aa64isar0_el1",  CPENC (3,0,0,6,0),      F_REG_READ,             AARCH64_NO_FEATURES)
   SYSREG ("id_aa64isar1_el1",  CPENC (3,0,0,6,1),      F_REG_READ,             AARCH64_NO_FEATURES)
   SYSREG ("id_aa64isar2_el1",  CPENC (3,0,0,6,2),      F_REG_READ,             AARCH64_NO_FEATURES)