arm64: zynqmp: Use assigned-clock-rates for setting up clock in SOM

With limited low level configuration done via psu-init only IPs connected
on SOM are initialized and configured. All IPs connected to carrier card
are not initialized. There is a need to do proper reset, pin configuration
and also clock setting.
The patch targets the last part which is setting up proper clock for USBs
and SDs which on kr260 and kv260-revB boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index b0700022a426830a2e80cdabda38cd15a1a6c635..0c4d2c9d36a1e03903153dcf1e4a9b2fe17c2197 100644 (file)
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -238,10 +238,12 @@
 
 &sdhci0 {
        clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
+       assigned-clocks = <&zynqmp_clk SDIO0_REF>;
 };
 
 &sdhci1 {
        clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
+       assigned-clocks = <&zynqmp_clk SDIO1_REF>;
 };
 
 &spi0 {
@@ -278,10 +280,12 @@
 
 &usb0 {
        clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+       assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
 };
 
 &usb1 {
        clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+       assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
 };
 
 &watchdog0 {

diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index 738363d534c59035b61f5815f00cba9c08e86477..35afdab79b94f61a76a1b9150714b2f17f8d18e5 100644 (file)
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@@ -135,6 +135,7 @@
        phy-names = "usb3-phy";
        phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
        reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
+       assigned-clock-rates = <250000000>, <20000000>;
 
        usbhub0: usb-hub@2d { /* u43 */
                i2c-bus = <&usbhub_i2c0>;
@@ -162,6 +163,7 @@
        phy-names = "usb3-phy";
        phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
        reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
+       assigned-clock-rates = <250000000>, <20000000>;
 
        usbhub1: usb-hub@2d { /* u84 */
                i2c-bus = <&usbhub_i2c1>;

diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 7cfa4b00ec9e2db977aee764c58d7c8181a1d95a..4ea9de5c02d705da91cd9eef3df3be48c639132a 100644 (file)
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -107,6 +107,7 @@
        pinctrl-0 = <&pinctrl_usb0_default>;
        phy-names = "usb3-phy";
        phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+       assigned-clock-rates = <250000000>, <20000000>;
 
        usb5744: usb-hub@2d { /* u43 */
                status = "okay";
@@ -138,6 +139,7 @@
        clk-phase-sd-hs = <126>, <60>;
        clk-phase-uhs-sdr25 = <120>, <60>;
        clk-phase-uhs-ddr50 = <126>, <48>;
+       assigned-clock-rates = <187498123>;
 };
 
 &gem3 { /* required by spec */

diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 59bdd73fa9e165a30d7a85a129effc19269577ba..a8f569414776d7dd1702d898dcb7857ef6789f75 100644 (file)
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -193,6 +193,7 @@
        disable-wp;
        bus-width = <8>;
        xlnx,mio-bank = <0>;
+       assigned-clock-rates = <187498123>;
 };
 
 &spi1 { /* MIO6, 9-11 */