drm/i915/pcode: drop fast wait from snb_pcode_write_timeout()

Only use the ms granularity wait in snb_pcode_write_timeout(), primarily
to better align with the xe driver, which also only has the millisecond
wait.

Use an arbitrary 250 us fast wait before the specified ms wait, and have
snb_pcode_write() default to 1 ms.

This means snb_pcode_write() and snb_pcode_write_timeout() will always
be sleeping functions. There should not be any atomic users for pcode
writes though, and any display code using pcode via xe has already been
non-atomic. The uncore wait will do a might_sleep() annotation that
should catch any problems.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/ba86280f53cea2d020308db35f1ecbd615d07d8a.1750678991.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3f68098f27c9a2566cb8a03e1589842d7901841b..8c5c9ebb75c1f41811d76c762f12a3f4705b15ee 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2148,7 +2148,7 @@ static void bxt_set_cdclk(struct intel_display *display,
                 */
                ret = snb_pcode_write_timeout(&dev_priv->uncore,
                                              HSW_PCODE_DE_WRITE_FREQ_REQ,
-                                             0x80000000, 150, 2);
+                                             0x80000000, 2);
 
        if (ret) {
                drm_err(display->drm,
@@ -2188,8 +2188,7 @@ static void bxt_set_cdclk(struct intel_display *display,
                 */
                ret = snb_pcode_write_timeout(&dev_priv->uncore,
                                              HSW_PCODE_DE_WRITE_FREQ_REQ,
-                                             cdclk_config->voltage_level,
-                                             150, 2);
+                                             cdclk_config->voltage_level, 2);
        }
        if (ret) {
                drm_err(display->drm,

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 0f1848b970a77c236d0be5673f21c1adc7bee88a..109be9801ba19fc3c235988235eceb78300b2bc4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -486,8 +486,7 @@ static void icl_tc_cold_exit(struct intel_display *display)
        int ret, tries = 0;
 
        while (1) {
-               ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0,
-                                             250, 1);
+               ret = snb_pcode_write(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0);
                if (ret != -EAGAIN || ++tries == 3)
                        break;
                msleep(1);

diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index 3db2ba439bb57f0f456d9ec488be80d1b64ba3a1..b7e9b4ee1425b31b0fc647da829f0213a801f01a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -110,13 +110,12 @@ int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
 }
 
 int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
-                           int fast_timeout_us, int slow_timeout_ms)
+                           int timeout_ms)
 {
        int err;
 
        mutex_lock(&uncore->i915->sb_lock);
-       err = __snb_pcode_rw(uncore, mbox, &val, NULL,
-                            fast_timeout_us, slow_timeout_ms, false);
+       err = __snb_pcode_rw(uncore, mbox, &val, NULL, 250, timeout_ms, false);
        mutex_unlock(&uncore->i915->sb_lock);
 
        if (err) {

diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 8d2198e294225a16fd5c91795101d4ea5cc1ba23..401ce27f72d499947f3370e35f3ea8cf50a85840 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -11,10 +11,9 @@
 struct intel_uncore;
 
 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
-int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
-                           int fast_timeout_us, int slow_timeout_ms);
+int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val, int timeout_ms);
 #define snb_pcode_write(uncore, mbox, val) \
-       snb_pcode_write_timeout(uncore, mbox, val, 500, 0)
+       snb_pcode_write_timeout((uncore), (mbox), (val), 1)
 
 int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
                      u32 reply_mask, u32 reply, int timeout_base_ms);

diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
index a473aa6697d0c2107f8922431d97e3dc416205bf..32da708680c23b443736d5f06373cf77bbb97ac0 100644 (file)
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
@@ -10,11 +10,9 @@
 #include "xe_pcode.h"
 
 static inline int
-snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
-                       int fast_timeout_us, int slow_timeout_ms)
+snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val, int timeout_ms)
 {
-       return xe_pcode_write_timeout(__compat_uncore_to_tile(uncore), mbox, val,
-                                     slow_timeout_ms ?: 1);
+       return xe_pcode_write_timeout(__compat_uncore_to_tile(uncore), mbox, val, timeout_ms);
 }
 
 static inline int