target/mips: Add missing 'break' for a case of MTHC0 handling

This was found by GCC 8.3 static analysis.

Fixes: 5fb2dcd1792
Reported-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1563220847-14630-3-git-send-email-aleksandar.markovic@rt-rk.com>

diff --git a/target/mips/translate.c b/target/mips/translate.c
index f96f141cdf25cae400d3c3456134bd7a774d50e3..cce1f125900b6f7d5b365e8faab58ab26c5ea6ca 100644 (file)
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6745,6 +6745,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         default:
             goto cp0_unimplemented;
         }
+        break;
     case CP0_REGISTER_17:
         switch (sel) {
         case 0: