]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
amd-xgbe: Add XGBE_XPCS_ACCESS_V3 support to xgbe_pci_probe()
authorRaju Rangoju <Raju.Rangoju@amd.com>
Fri, 9 May 2025 15:53:24 +0000 (21:23 +0530)
committerPaolo Abeni <pabeni@redhat.com>
Tue, 13 May 2025 11:29:41 +0000 (13:29 +0200)
A new version of XPCS access routines have been introduced, add the
support to xgbe_pci_probe() to use these routines.

Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20250509155325.720499-5-Raju.Rangoju@amd.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
drivers/net/ethernet/amd/xgbe/xgbe-common.h
drivers/net/ethernet/amd/xgbe/xgbe-pci.c
drivers/net/ethernet/amd/xgbe/xgbe.h

index e3d33f5b9642704324ecd1672875a3d81badec6e..e1296cbf4ff309893233fcc648386e92892962d4 100644 (file)
 #define PCS_V2_RV_WINDOW_SELECT                0x1064
 #define PCS_V2_YC_WINDOW_DEF           0x18060
 #define PCS_V2_YC_WINDOW_SELECT                0x18064
+#define PCS_V3_RN_WINDOW_DEF           0xf8078
+#define PCS_V3_RN_WINDOW_SELECT                0xf807c
+
+#define PCS_RN_SMN_BASE_ADDR           0x11e00000
+#define PCS_RN_PORT_ADDR_SIZE          0x100000
 
 /* PCS register entry bit positions and sizes */
 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
index d36446e76d0a42bee2636dbe76b70f2e860da96d..718534d3065139f95e277d0b77c3c1df18e3eef9 100644 (file)
@@ -9,6 +9,7 @@
 #include <linux/device.h>
 #include <linux/pci.h>
 #include <linux/log2.h>
+#include "xgbe-smn.h"
 
 #include "xgbe.h"
 #include "xgbe-common.h"
@@ -98,14 +99,14 @@ out:
 
 static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
-       struct xgbe_prv_data *pdata;
-       struct device *dev = &pdev->dev;
        void __iomem * const *iomap_table;
-       struct pci_dev *rdev;
+       unsigned int port_addr_size, reg;
+       struct device *dev = &pdev->dev;
+       struct xgbe_prv_data *pdata;
        unsigned int ma_lo, ma_hi;
-       unsigned int reg;
-       int bar_mask;
-       int ret;
+       struct pci_dev *rdev;
+       int bar_mask, ret;
+       u32 address;
 
        pdata = xgbe_alloc_pdata(dev);
        if (IS_ERR(pdata)) {
@@ -181,6 +182,10 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
                        /* Yellow Carp devices do not need rrc */
                        pdata->vdata->enable_rrc = 0;
                        break;
+               case XGBE_RN_PCI_DEVICE_ID:
+                       pdata->xpcs_window_def_reg = PCS_V3_RN_WINDOW_DEF;
+                       pdata->xpcs_window_sel_reg = PCS_V3_RN_WINDOW_SELECT;
+                       break;
                default:
                        pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
                        pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
@@ -193,7 +198,22 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
        pci_dev_put(rdev);
 
        /* Configure the PCS indirect addressing support */
-       reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
+       if (pdata->vdata->xpcs_access == XGBE_XPCS_ACCESS_V3) {
+               reg = XP_IOREAD(pdata, XP_PROP_0);
+               port_addr_size = PCS_RN_PORT_ADDR_SIZE *
+                                XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
+               pdata->smn_base = PCS_RN_SMN_BASE_ADDR + port_addr_size;
+
+               address = pdata->smn_base + (pdata->xpcs_window_def_reg);
+               ret = amd_smn_read(0, address, &reg);
+               if (ret) {
+                       pci_err(pdata->pcidev, "Failed to read data\n");
+                       goto err_pci_enable;
+               }
+       } else {
+               reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
+       }
+
        pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
        pdata->xpcs_window <<= 6;
        pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
index 44ba6b02cdeb294d062db73e1a10810a0397bc39..6359bb87dc13e3d58078f2754b535a75b2fec29e 100644 (file)
 /* XGBE PCI device id */
 #define XGBE_RV_PCI_DEVICE_ID  0x15d0
 #define XGBE_YC_PCI_DEVICE_ID  0x14b5
+#define XGBE_RN_PCI_DEVICE_ID  0x1630
 
  /* Generic low and high masks */
 #define XGBE_GEN_HI_MASK       GENMASK(31, 16)